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C-Boot ROM Description
6.6.15.6 C-Boot ROM I2C Boot Mode
The I2C bootloader expects an 8-bit wide I2C-compatible EEPROM device to be present at address 0x50
on the I2C-A bus as indicated in
protocol, as described in this section, with a 16-bit base address architecture.
Control
subsystem
The I2C loader uses following pins:
•
SDAA on GPIO 32
•
SCLA on GPIO 33
If the download is to be performed from a device other than an EEPROM, then that device must be set up
to operate in the slave mode and mimic the I2C EEPROM. Immediately after entering the I2C boot
function, the GPIO pins are configured for I2C-A operation and the I2C is initialized. The following
requirements must be met when booting from the I2C module:
•
The input frequency to the device must be in the appropriate range.
•
The EEPROM must be at slave address 0x50.
650
ROM Code and Peripheral Booting
Figure
6-23. The EEPROM must adhere to conventional I2C EEPROM
Figure 6-23. EEPROM Device at Address 0x50
SDA
SDAA
SCLA
Copyright © 2012–2019, Texas Instruments Incorporated
SCL
SDA
SCL
Slave Address
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
I2C
EEPROM
0x50
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