Set The Srg Frame-Synchronization Period And Pulse Width; Data Clocked Externally Using A Rising Edge And Sampled By The Mcbsp Receiver On A Falling Edge; Frame Of Period 16 Clkg Periods And Active Width Of 2 Clkg Periods; Register Bits Used To Set Srg Frame-Synchronization Period And Pulse Width - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Transmitter Configuration
Figure 15-58. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a
Internal
CLKR
DR

15.9.17 Set the SRG Frame-Synchronization Period and Pulse Width

Table 15-65. Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width
Register Bit
SRGR2 11-0
SRGR1 15-8
15.9.17.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
The sample rate generator can produce a clock signal, CLKG, and a frame-synchronization signal, FSG. If
the sample rate generator is supplying receive or transmit frame synchronization, you must program the
bit fields FPER and FWID.
On FSG, the period from the start of a frame-synchronization pulse to the start of the next pulse is (FPER
+ 1) CLKG cycles. The 12 bits of FPER allow a frame-synchronization period of 1 to 4096 CLKG cycles,
which allows up to 4096 data bits per frame. When GSYNC = 1, FPER is a don't care value.
Each pulse on FSG has a width of (FWID + 1) CLKG cycles. The eight bits of FWID allow a pulse width of
1 to 256 CLKG cycles. It is recommended that FWID be programmed to a value less than the
programmed word length.
The values in FPER and FWID are loaded into separate down-counters. The 12-bit FPER counter counts
down the generated clock cycles from the programmed value (4095 maximum) to 0. The 8-bit FWID
counter counts down from the programmed value (255 maximum) to 0.
Figure 15-59 shows a frame-synchronization period of 16 CLKG periods (FPER = 15 or 00001111b) and a
frame-synchronization pulse with an active width of 2 CLKG periods (FWID = 1).
Figure 15-59. Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods
1
CLKG
FSG
1148
C28 Multichannel Buffered Serial Port (McBSP)
Falling Edge
Name Function
FPER Sample rate generator frame-synchronization period
For the frame-synchronization signal FSG, (FPER + 1)
determines the period from the start of a frame-
synchronization pulse to the start of the next frame-
synchronization pulse.
Range for (FPER + 1):
FWID Sample rate generator frame-synchronization pulse width
This field plus 1 determines the width of each frame-
synchronization pulse on FSG.
Range for (FWID + 1):
2 3 4 5 6 7
Frame-synchronization period: (FPER+1) x CLKG
Frame-synchronization pulse width: (FWID + 1) x CLKG
Copyright © 2012–2019, Texas Instruments Incorporated
Data setup
B7
1 to 4096 CLKG cycles.
1 to 256 CLKG cycles.
8 9 10 11 12 13
SPRUHE8E – October 2012 – Revised November 2019
Data hold
B6
Type Reset Value
R/W 0000 0000 0000
R/W 0000 0000
14 15 16 17 18 19
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