Cortex General-Purpose Registers 0-12 (R0-R12); Stack Pointer Register (Sp); Cortex General-Purpose Registers 0-12 (R0-R12) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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24.4.4 Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in
registers are not memory mapped and are accessed by register name rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution in
thread mode and handler mode. Debug access can differ.
24.4.4.1 Cortex General-Purpose Registers 0-12 (Core R0-R12)
The Core registers (Rn) are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24-3. Cortex General-Purpose Registers 0-12 (R0-R12) Field Descriptions
Bit Field
31-0 DATA
24.4.4.2 Stack Pointer (SP)
The stack pointer (SP) is register R13. In Thread mode, the function of this register changes depending on
the ASP bit in the CONTROL register. When the ASP bit is clear, this register is the main stack pointer
(MSP). When the ASP bit is set, this register is the process stack pointer (PSP). On reset, the ASP bit is
clear, and the processor loads the MSP with the value from address 0x0000.0000. The MSP can only be
accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24-4. Cortex General-Purpose Registers 0-12 (R0-R12) Field Descriptions
Bit Field
31-0 SP
SPRUHE8E – October 2012 – Revised November 2019
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Figure 24-3. Cortex General-Purpose Registers 0-12 (R0-R12)
Value Description
Register data.
Figure 24-4. Stack Pointer Register (SP)
Value Description
Stack pointer address
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DATA
R/W
SP
R/W
Programming Model
Figure 24-2. The core
1609
Cortex-M3 Processor
0
0