Clock Stop Mode Timing Diagrams; Effects Of Clkstp, Clkxp, And Clkrp On The Clock Scheme - Texas Instruments Concerto F28M36 Series Technical Reference Manual

SPI Operation Using the Clock Stop Mode
Table 15-14. Bits Used to Enable and Configure the Clock Stop Mode (continued)
Bit Field
XPHASE bit of XCR2
RPHASE bit of RCR2
XFRLEN1 bits of XCR1
RFRLEN1 bits of RCR1
XWDLEN1 bits of XCR1
RWDLEN1 bits of RCR1
Table 15-15. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
Bit Settings
CLKSTP = 00b or 01b
CLKXP = 0 or 1
CLKRP = 0 or 1
CLKSTP = 10b
CLKXP = 0
CLKRP = 0
CLKSTP = 11b
CLKXP = 0
CLKRP = 1
CLKSTP = 10b
CLKXP = 1
CLKRP = 0
CLKSTP = 11b
CLKXP = 1
CLKRP = 1

15.7.4 Clock Stop Mode Timing Diagrams

The timing diagrams for the four possible clock stop mode configurations are shown here. Notice that the
frame-synchronization signal used in clock stop mode is active throughout the entire transmission as a
slave-enable signal. Although the timing diagrams show 8-bit transfers, the packet length can be set to 8,
12, 16, 20, 24, or 32 bits per packet. The receive packet length is selected with the RWDLEN1 bits of
RCR1, and the transmit packet length is selected with the XWDLEN1 bits of XCR1. For clock stop mode,
the values of RWDLEN1 and XWDLEN1 must be the same because the McBSP transmit and receive
circuits are synchronized to a single clock.
NOTE: Even if multiple words are consecutively transferred, the CLKX signal is always stopped and
the FSX signal returns to the inactive state after a packet transfer. When consecutive packet
transfers are performed, this leads to a minimum idle time of two bit-periods between each
packet transfer.
1110
C28 Multichannel Buffered Serial Port (McBSP)
Description
You must use a single-phase transmit frame (XPHASE = 0).
You must use a single-phase receive frame (RPHASE = 0).
You must use a transmit frame length of 1 serial word (XFRLEN1 = 0).
You must use a receive frame length of 1 serial word (RFRLEN1 = 0).
The XWDLEN1 bits determine the transmit packet length. XWDLEN1 must be equal to
RWDLEN1 because in the clock stop mode. The McBSP transmit and receive circuits
are synchronized to a single clock.
The RWDLEN1 bits determine the receive packet length. RWDLEN1 must be equal to
XWDLEN1 because in the clock stop mode. The McBSP transmit and receive circuits
are synchronized to a single clock.
Clock Scheme
Clock stop mode disabled. Clock enabled for non-SPI mode.
Low inactive state without delay: The McBSP transmits data on the rising edge of CLKX and
receives data on the falling edge of MCLKR.
Low inactive state with delay: The McBSP transmits data one-half cycle ahead of the rising
edge of CLKX and receives data on the rising edge of MCLKR.
High inactive state without delay: The McBSP transmits data on the falling edge of CLKX and
receives data on the rising edge of MCLKR.
High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling
edge of CLKX and receives data on the falling edge of MCLKR.
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SPRUHE8E – October 2012 – Revised November 2019
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