Master Reset Cause (Mresc) Register; Master Reset Cause (Mresc) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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1.13.3.3 Master Reset Cause (MRESC) Register

31 30
ACIBERRNMI C28NMIWDRS
T
R-0 R/W-0
23
15
7 6
Reserved
R-0:0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-63. Master Reset Cause (MRESC) Register Field Descriptions
Bit Field
31 ACIBERRNMI
30 C28NMIWDRST
29 M3BISTERRNMI
28 C28BISTERRNMI
27 C28PIENMI
26-25 HWBIST
SPRUHE8E – October 2012 – Revised November 2019
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Figure 1-52. Master Reset Cause (MRESC) Register
29 28
M3BISTERRN C28BISTERRN
MI MI
R/w-0 R/w-0
Reserved
R-0
5 4
WDT1 SW
R/W-0 R/W-0
Value Description
ACIB Error NMI Unserviced
0 No M3 NMIWD device reset since the previous POR.
Writing a "0" to this bit clears it.
1 CIB access signals stuck condition caused an NMI which was not serviced by the CPU and that
caused an NMIWD reset.
C28 NMIWD Reset NMI Unserviced
0 No M3 NMIWD device reset since the previous POR.
Writing a "0" to this bit clears it.
1 C28 NMIWD errored or timed out and triggered a M3 NMI and this triggered the M3 NMIWD. M3
did not respond to the NMI and the M3 NMIWD fired a reset.
M3 BIST Error NMI Unserviced
0 M3 did not respond to the NMI and the NMIWD fired a reset. If '0' then there was NMIWD event
that caused a device reset since the previous POR
Writing a '0' to this bit clears this bit
1 If set, indicates that M3 hardware BIST errored or timed out and triggered a M3 NMI and this
triggered the M3 NMIWD
C28 BIST Error NMI Unserviced
0 M3 did not respond to the NMI and the NMIWD fired a reset. If '0' then there was NMIWD event
that caused a device reset since the previous POR
Writing a '0' to this bit clears this bit
1 If set, indicates that C28 hardware BIST errored or timed out and triggered a M3 NMI and this
triggered the M3 NMIWD.
C28 PIE NMI Error Unserviced
0 No M3 NMIWD event that caused a device reset since the previous POR.
Writing a "0" to this bit clears it.
1 C28 PIE NMI vector fetch error triggered a M3 NMI and this triggered the M3 NMIWD. M3 did not
respond to the NMI and the NMIWD fired a reset.
HWBIST Unserviced. Can be used by the boot ROM to decide to jump to appropriate code
0 If '00' then there was no M3 HWBIST reset issued to the M3 CPU.
Writing a '00' to these bits clears these bits
1 If set to 11, indicates that M3 CPU HWBIST has run to completion and issued a reset to the M3
CPU.
Copyright © 2012–2019, Texas Instruments Incorporated
27 26
C28PIENMI
R/W-0
Reserved
R-0:0
3 2
WDT0 Reserved
R/W-0 R-0:0
System Control Registers
25 24
HWBIST EXTGPIO
R/w-0 R/W-0
17 16
MCLKNMI
R/W-0
8
1 0
POR XRS
R/W-1 R/W-1
System Control and Interrupts
193