Table of Contents
Advertisement
www.ti.com
15.2.6 Frame Frequency
The frame frequency is determined by the period between frame-synchronization pulses and is defined as
shown by Example 1.
Equation 1: McBSP Frame Frequency
Frame Frequency +
The frame frequency can be increased by decreasing the time between frame-synchronization pulses
(limited only by the number of bits per frame). As the frame transmit frequency increases, the inactivity
period between the data packets for adjacent transfers decreases to zero.
15.2.7 Maximum Frame Frequency
The minimum number of clock cycles between frame synchronization pulses is equal to the number of bits
transferred per frame. The maximum frame frequency is defined as shown by Example 2.
Equation 2: McBSP Maximum Frame Frequency
Figure 15-8
shows the McBSP operating at maximum packet frequency. At maximum packet frequency,
the data bits in consecutive packets are transmitted contiguously with no inactivity between bits.
Figure 15-8. McBSP Operating at Maximum Packet Frequency
CLK(R/X)
FS(R/X)
A2
D(R/X)
If there is a 1-bit data delay as shown in this figure, the frame-synchronization pulse overlaps the last bit
transmitted in the previous frame. Effectively, this permits a continuous stream of data, making frame-
synchronization pulses redundant. Theoretically, only an initial frame-synchronization pulse is required to
initiate a multipacket transfer.
The McBSP supports operation of the serial port in this fashion by ignoring the successive frame-
synchronization pulses. Data is clocked into the receiver or clocked out of the transmitter during every
clock cycle.
NOTE: For XDATDLY = 0 (0-bit data delay), the first bit of data is transmitted asynchronously to the
internal transmit clock signal (CLKX). For more details, see
Transmit Data Delay.
15.3 Frame Phases
The McBSP allows you to configure each frame to contain one or two phases. The number of words and
the number of bits per word can be specified differently for each of the two phases of a frame, allowing
greater flexibility in structuring data transfers. For example, you might define a frame as consisting of one
phase containing two words of 16 bits each, followed by a second phase consisting of 10 words of 8 bits
each. This configuration permits you to compose frames for custom applications or, in general, to
maximize the efficiency of data transfers.
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Number of Clock Cycles Between Frame- Sync Pulses
Maximum Frame Frequency +
A1
A0
B7
B6
Copyright © 2012–2019, Texas Instruments Incorporated
Clock Frequency
Clock Frequency
Number of Bits Per Frame
B5
B4
B3
B2
B1
Section
C28 Multichannel Buffered Serial Port (McBSP)
Clocking and Framing Data
B0
C7
C6
15.9.12, Set the
1081
Advertisement
Chapters
Table of Contents
