I2C Slave Address Register (I2Csar); I2C Own Address Register (I2Coar); Dependency Of Delay D On The Divide-Down Value Ipsc; I2C Slave Address Register (I2Csar) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

I2C Module Registers

14.5.8 I2C Slave Address Register (I2CSAR)

The I2C slave address register (I2CSAR) is a register for storing the next slave address that will be
transmitted by the I2C module when it is a master. It is a 16-bit register with the format shown in
Figure 14-25. As described in
address. When the I2C module is not using the free data format (FDF = 0 in I2CMDR), it uses this
address to initiate data transfers with a slave or slaves. When the address is nonzero, the address is for a
particular slave. When the address is 0, the address is a general call to all slaves. If the 7-bit addressing
mode is selected (XA = 0 in I2CMDR), only bits 6-0 of I2CSAR are used; write 0s to bits 9-7.
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-16. I2C Slave Address Register (I2CSAR) Field Descriptions
Bit Field Value
15-10 Reserved
9-0 SAR
00h-7Fh
000h-3FFh

14.5.9 I2C Own Address Register (I2COAR)

The I2C own address register (I2COAR) is a 16-bit register.
and Table 14-17 describes its bit fields. The I2C module uses this register to specify its own slave
address, which distinguishes it from other slaves connected to the I2C-bus. If the 7-bit addressing mode is
selected (XA = 0 in I2CMDR), only bits 6-0 are used; write 0s to bits 9-7.
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-17. I2C Own Address Register (I2COAR) Field Descriptions
Bit Field Value
15-10 Reserved
9-0 OAR
00h-7Fh
000h-3FFh
1068
C28 Inter-Integrated Circuit Module
Table 14-15. Dependency of Delay d on the Divide-
Down Value IPSC
IPSC
0
1
Greater than 1
Table 14-16, the SAR field of I2CSAR contains a 7-bit or 10-bit slave
Figure 14-25. I2C Slave Address Register (I2CSAR)
10 9
Description
These reserved bit locations are always read as zeros. A value written to this field has no effect.
In 7-bit addressing mode (XA = 0 in I2CMDR):
Bits 6-0 provide the 7-bit slave address that the I2C module transmits when it is in the master-
transmitter mode. Write 0s to bits 9-7.
In 10-bit addressing mode (XA = 1 in I2CMDR):
Bits 9-0 provide the 10-bit slave address that the I2C module transmits when it is in the master-
transmitter mode.
Figure 14-26. I2C Own Address Register (I2COAR)
10 9
Description
These reserved bit locations are always read as zeros. A value written to this field has no effect.
In 7-bit addressing mode (XA = 0 in I2CMDR):
Bits 6-0 provide the 7-bit slave address of the I2C module. Write 0s to bits 9-7.
In 10-bit addressing mode (XA = 1 in I2CMDR):
Bits 9-0 provide the 10-bit slave address of the I2C module.
Copyright © 2012–2019, Texas Instruments Incorporated
d
7
6
5
SAR
R/W-3FFh
Figure 14-26 shows the format of I2COAR,
OAR
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
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