Master Single Receive - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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SPRUHE8E – October 2012 – Revised November 2019
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Figure 22-8. Master Single RECEIVE
Write Slave
Address and
Receive Bit
to I2CMSA
Read I2CMCS
NO
BUSBSY bit=0?
Write 0111
to I2CMCS
Read I2CMCS
NO
BUSY bit=0?
NO
Error Service ERROR bit=0?
Read data from
I2CMDR
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Idle
Sequence may be
omitted in a Single
Master system
YES
YES
YES
Idle
M3 Inter-Integrated Circuit (I2C) Interface
Functional Description
1529