Dead-Band Delay Values In Μs As A Function Of Dbfed And Dbred - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED)
delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit
registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is
delayed by. For example, the formula to calculate falling-edge-delay and rising-edge-delay are:
FED = DBFED × T
RED = DBRED × T
Where T is the period of TBCLK, the prescaled version of SYSCLKOUT.
TBCLK
For convenience, delay values for various TBCLK options are shown in
Table 7-17. Dead-Band Delay Values in μS as a Function of DBFED and DBRED
Dead-Band Value
DBFED, DBRED
1
5
10
100
200
400
500
600
700
800
900
1000
When half-cycle clocking is enabled, the formula to calculate the falling-edge-delay and rising-edge-delay
becomes:
FED = DBFED × T
RED = DBRED × T
SPRUHE8E – October 2012 – Revised November 2019
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TBCLK
TBCLK
TBCLK = SYSCLKOUT/1
0.01 μS
0.06 μS
0.13 μS
1.25 μS
2.50 μS
5.00 μS
6.25 μS
7.50 μS
8.75 μS
10.00 μS
11.25 μS
12.50 μS
/2
TBCLK
/2
TBCLK
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Table 7-17.
Dead-Band Delay in μS
TBCLK = SYSCLKOUT /2
0.03 μS
0.13μS
0.25 μS
2.50 μS
5.00 μS
10.00 μS
12.50 μS
15.00 μS
17.50 μS
20.00 μS
22.50 μS
25.00 μS
C28 Enhanced Pulse Width Modulator (ePWM) Module
ePWM Submodules
TBCLK = SYSCLKOUT/4
0.05 μS
0.25 μS
0.50 μS
5.00 μS
10.00 μS
20.00 μS
25.00 μS
30.00 μS
35.00 μS
40.00 μS
45.00 μS
50.00 μS
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