Cepirtwprd Register; Cepistatus Register; Memprot Register; Cepirtwprd Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Register Descriptions

17.11.39 CEPIRTWPRD Register

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
FiKEY
31-0
EPIRTWPRD

17.11.40 CEPISTATUS Register

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-2
Reserved
1
MEMPROTERR
0
RTWTIMEOUT

17.11.41 MEMPROT Register

31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1314
External Peripheral Interface (EPI)
Figure 17-66. CEPIRTWPRD Register
Table 17-52. CEPIRTWPRD Register Field Descriptions
Value
Description
When EPIRTWCNT value becomes equal to value into this field, TIMEOUT occurs and the
TIMEOUT status flag in CEPISTATUS register gets set. Program this field based on the application
which needs dedicated access to external device from the control subsystem via EPI.
Note: Do not try to program this field when the GRAB bit in the CEPIRTWCFG register is set to '1'.
Program this field first and then set the GRAB bit.
Figure 17-67. CEPISTATUS Register
Reserved
R-0
Table 17-53. CEPISTATUS Register Field Descriptions
Value
Description
Reserved
Status bit for Memory Protection violation by control subsystem (C28x-CPU/C28x-DMA).
0
Memory protection violation has not occurred.
1
Memory protection violation occurred. C28x-CPU or C28x-DMA tried to write into external memory
space which was protected. An interrupt has been generated to C28x CPU.
Status bit for RTW time out. Writing a '1' to this field clears the status to '0'
0
TIMEOUT has not occurred.
1
C28x software didn't release the GRAB with in programmed time period hence TIMEOUT has
happened and an interrupt has been generated to C28x CPU.
Figure 17-68. MEMPROT Register
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
EPIRTWPRD
0xFFFF_FFFF
Reserved
R-0
Reserved
8
7
6
5
CS3PROT
CS2PROT
R/W-0
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
2
3
2
1
MEMPROTER
RTWTIMEOUT
R
R/W-1
R/W-1
4
3
2
1
CS1PROT
CS0PROT
R/W-0
R/W-0
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0
16
0
16
0

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