Master Subsystem Non-Maskable Interrupt (Mnmi) Module - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Exceptions and Interrupts Control

unless the CPU is decoding the erroneous instruction fetched

For more details on how the remaining exceptions are generated by the Cortex-M3 CPU, refer to the NVIC

section of the Cortex-M3 Peripherals chapter.

Refer to the Boot ROM chapter for more details on how boot ROM handles HARDFAULT exceptions if it

occurs during boot ROM execution.

On the master subsystem all the below errors generate a BUSFAULT.

RAMUNCERR - RAM Uncorrectable error. This is a double bit error generated by the RAM wrapper

logic as a bus error. Refer to the Internal Memory chapter of this document for more details.

RAMACCVIOL - Ram Access violation. Refer to the Internal Memory chapter for more details on what

can generate this error.

FLASHUNCERR - Flash Uncorrectable error. Refer to the Internal Memory chapter for more details on

1.5.3 Master Subsystem Non-Maskable Interrupt (MNMI) Module

The master subsystem has the capability of detecting all serious errors that could occur in the entire

system including all the subsystems, and inform the main CPU core about the error. An NMI exception to

the M3 CPU on the master subsystem will be generated only when at least one or more of the below NMI

error sources become active. More details on each of the sources is given in

1. Clock fail condition detected

2. External GPIO input signal is requesting an NMI

3. Error condition is generated on a C28 PIE NMI vector fetch

4. CNMIWD timed out and issued a reset to the C28 CPU

5. Stuck condition is detected on the ACIB INTS or READY signals (referred to as ACIBERR in this

section of this spec)

6. Voltage Regulator warning NMI

All these NMI sources are "OR-ed" to generate the NMI input to the M3 NVIC. The NMI triggers a

MNMIWD counter running at the master subsystem frequency. The MNMIWD counter will stop counting

only if all the pending NMIs are acknowledged by clearing the pending flags in the MNMIFLG register. If

the pending NMI is not acknowledged before the MNMIWD counter reaches the value programmed in the

NMI WatchDog period register (MNMIWDPRD), an NMIWD reset is generated to the master subsystem,

which will reset the entire device.

shows different sources that can trigger an NMI to the Cortex-M3 on the master subsystem and

the registers associated with them.

System Control and Interrupts

SPRUHE8E – October 2012 – Revised November 2019

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