Gpio Port D Mux 1 (Gpdmux1) Register; Gpio Port D Mux 1 (Gpdmux1) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 4-56. GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions (continued)
Bit Field
1-0 GPIO80
4.2.7.7

GPIO Port D MUX 1 (GPDMUX1) Register

The GPIO Port D MUX 1 (GPDMUX1) register is shown and described in the figure and table below.
31 30
GPIO111
R/W-0
23 22
GPIO107
R/W-0
15 14
GPIO103
R/W-0
7 6
GPIO99
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-57. GPIO Port D MUX 1 (GPDMUX1) Register Field Descriptions
Bit Field
31-30 GPIO111
29-28 GPIO110
27-26 GPIO109
25-24 GPIO108
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Configure this pin as:
00 GPIO 80 - general purpose I/O 80 (default)
01 Reserved
10 Reserved
11 Reserved
Figure 4-48. GPIO Port D MUX 1 (GPDMUX1) Register
29 28
GPIO110
R/W-0
21 20
GPIO106
R/W-0
13 12
GPIO102
R/W-0
5 4
GPIO98
R/W-0
Value Description
Configure this pin as:
00 GPIO 111 - general purpose I/O 111 GPIO (default)
01 Reserved
10 EQEP2B
11 EQEP3I
Configure this pin as:
00 GPIO 110 - general purpose I/O 110 GPIO (default)
01 Reserved
10 EQEP2A
11 EQEP3S
Configure this pin as:
00 GPIO 109 - general purpose I/O 109 GPIO (default)
01 EQEP1I
10 Reserved
11 Reserved
Configure this pin as:
00 GPIO 108 - general purpose I/O 108 GPIO (default)
01 EQEP1S
10 Reserved
11 Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
C28 General-Purpose Input/Output (GPIO)
27 26
GPIO109
R/W-0
19 18
GPIO105
R/W-0
11 10
GPIO101
R/W-0
3 2
GPIO97
R/W-0
General-Purpose Input/Output (GPIO)
25 24
GPIO108
R/W-0
17 16
GPIO104
R/W-0
9 8
GPIO100
R/W-0
1 0
GPIO96
R/W-0
415