Usb Power Management Register (Usbpower), Offset 0X001; Power Management Register (Usbpower) In Otg A/Host Mode; Power Management Register (Usbpower) In Otg B/Device Mode; Power Management Register (Usbpower) In Otg A/Host Mode Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions

18.5.2 USB Power Management Register (USBPOWER), offset 0x001

The power management 8-bit register (USBPOWER) is used for controlling SUSPEND and RESUME
signaling, and some basic operational aspects of the USB controller.
Mode(s): OTG A or Host
USBPOWER in OTG A/Host Mode is shown in
Figure 18-3. Power Management Register (USBPOWER) in OTG A/Host Mode
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-6. Power Management Register (USBPOWER) in OTG A/Host Mode Field Descriptions
Bit Field
7-4 Reserved
3 RESET
2 RESUME
1 SUSPEND
0 PWRDNPHY
USBPOWER in OTG B/Device Mode is shown in
Figure 18-4. Power Management Register (USBPOWER) in OTG B/Device Mode
7 6
ISOUPDATE SOFTCONN
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-7. Power Management Register (USBPOWER) in OTG B/Device Mode Field Descriptions
Bit Field
7 ISOUPDATE
6 SOFTCONN
5-4 Reserved
1338
M3 Universal Serial Bus (USB) Controller
OTG B or Device
4
R-0
Value Description
0 Reserved
RESET signaling.
0 Ends RESET signaling on the bus.
1 Enables RESET signaling on the bus.
RESUME signaling. The bit should be cleared by software 20 ms after being set.
0 Ends RESUME signaling on the bus.
1 Enables RESUME signaling when the Device is in SUSPEND mode.
SUSPEND mode
0 No effect
1 Enables SUSPEND mode.
Power Down PHY
0 No effect
1 Powers down the internal USB PHY.
5 4
Reserved
R-0
Value Description
Isochronous Update
0 No effect
1 The USB controller waits for an SOF token from the time the TXRDY bit is set in the USBTXCSRLn
register before sending the packet. If an IN token is received before an SOF token, then a zero-
length data packet is sent.
Soft Connect/Disconnect
0 The USB D+/D- lines are tri-stated.
1 The USB D+/D- lines are enabled.
0 Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 18-3 and described in
3 2
RESET RESUME
R/W-0 R/W-0
Figure 18-4 and described in
3 2
RESET RESUME
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Table 18-6.
1 0
SUSPEND PWRDNPHY
R/W-1S R/W-0
Table 18-7.
1 0
SUSPEND PWRDNPHY
R-0 R/W-0
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