Gpio Alternate Peripheral Select (Gpioapsel) Register; Gpio Alternate Peripheral Select (Gpioapsel) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
4.1.6.18 GPIO Alternate Peripheral Select (GPIOAPSEL) Register, offset 0x530
The GPIOAPSEL register is used to access the M3 GPIO alternate peripheral muxing options. When
these bits are set, values of 0x0 - 0xF are valid values in the GPIOPCTL PMCx bit fields. See
Section 4.2.6 for alternate muxing options.
Figure 4-21. GPIO Alternate Peripheral Select (GPIOAPSEL) Register
31
15
7 6
APSEL7 APSEL6
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-22. GPIO Alternate Peripheral Select (GPIOAPSEL) Register Field Descriptions
Bit Field
31-8 Reserved
7 APSEL7
6 APSEL6
5 APSEL5
4 APSEL4
3 APSEL3
2 APSEL2
1 APSEL1
0 APSEL0
368
General-Purpose Input/Output (GPIO)
5 4
APSEL5 APSEL4
R/W-0 R/W-0
Value Description
Reserved
Alternate peripheral select 7
0 Alternate peripheral mode disabled
1 Alternate peripheral mode enable
Alternate peripheral select 6
0 Alternate peripheral mode disabled
1 Alternate peripheral mode enable
Alternate peripheral select 5
0 Alternate peripheral mode disabled
1 Alternate peripheral mode enable
Alternate peripheral select 4
0 Alternate peripheral mode disabled
1 Alternate peripheral mode enable
Alternate peripheral select 3
0 Alternate peripheral mode disabled
1 Alternate peripheral mode enable
Alternate peripheral select 2
0 Alternate peripheral mode disabled
1 Alternate peripheral mode enable
Alternate peripheral select 1
0 Alternate peripheral mode disabled
1 Alternate peripheral mode enable
Alternate peripheral select 0
Alternate peripheral mode disabled
Alternate peripheral mode enable
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
Reserved
R-0
3 2
APSEL3 APSEL2
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
8
1 0
APSEL1 APSEL0
R/W-0 R/W-0
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