Ssiris Register; Ssiris Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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20.5.2.7 SSIRIS Register (Offset = 18h) [reset = 8h]
SSIRIS is shown in
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SSI Raw Interrupt Status
31 30
23 22
15 14
7 6
RESERVED EOTRIS
R-0h R-0h
Bit Field
31-7 RESERVED
6 EOTRIS
5 DMATXRIS
4 DMARXRIS
3 TXRIS
2 RXRIS
SPRUHE8E – October 2012 – Revised November 2019
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Figure 20-16 and described in
Table.
Figure 20-16. SSIRIS Register
29 28
21 20
13 12
5 4
DMATXRIS DMARXRIS
R-0h R-0h
Table 20-10. SSIRIS Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 1h
R 0h
Copyright © 2012–2019, Texas Instruments Incorporated
Table 20-10.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
TXRIS RXRIS
R-1h R-0h
Description
Reserved
End of Transmit Raw Interrupt Status
Value Description
0 No interrupt.
1 The transmit FIFO is empty, and the last bit has been transmitted
out of the serializer.This bit is cleared when a 1 is written to the
EOTIC bit in the SSI Interrupt Clear (SSIICR) register.
Reset type: PER.RESET
SSI Transmit DMA Raw Interrupt Status
Value Description
0 No interrupt.
1 The transmit DMA has completed.This bit is cleared when a 1 is
written to the DMATXIC bit in the SSI Interrupt Clear (SSIICR)
register.
Reset type: PER.RESET
SSI Receive DMA Raw Interrupt Status
Value Description
0 No interrupt.
1 The receive DMA has completed.This bit is cleared when a 1 is
written to the DMARXIC bit in the SSI Interrupt Clear (SSIICR)
register.
Reset type: PER.RESET
SSI Transmit FIFO Raw Interrupt Status
Value Description
0 No interrupt.
1 The transmit FIFO is half empty or less. If the EOT bit in the
SSICR1 register is clear, If the EOT bit is set, the transmit FIFO is
empty, and the last bit has been transmitted out of the serializer.This
bit is cleared when the transmit FIFO is more than half full. (if the
EOT bit is clear) or when it has any data in it (if the EOT bit is set)
Reset type: PER.RESET
SSI Receive FIFO Raw Interrupt Status
Value Description
0 No interrupt.
1 The receive FIFO is half full or more.This bit is cleared when the
receive FIFO is less than half full.
Reset type: PER.RESET
M3 Synchronous Serial Interface (SSI)
SSI Registers
26 25
18 17
10 9
2 1
RTRIS
R-0h
24
16
8
0
RORRIS
R-0h
1467