Flash Prefetch Mode - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Table of Contents

Flash prefetch

5.3.8.2.2.1 Data Cache

Along with the prefetch mechanism, a data cache of 128 bits width is also implemented to improve data

space read and program space read performance. This data cache will not be filled by the prefetch

mechanism. When any kind of data-space read or program-space read is made by the CPU from an

address in the bank, and if the data corresponding to the requested address is not in the data cache, then

128 bits of data will be read from the bank and is loaded in the data cache. This data is eventually sent to

the CPU for processing. The starting address of the access from flash is automatically aligned to a 128-bit

boundary such that the requested address location is within the 128 bits to be read from the bank. By

default, this data cache is disabled and can be enabled by setting DATA_CACHE_EN bit in the

FRD_INTF_CTRL register.

Some other points to keep in mind when working with C28x flash:

Reads of the CSM password locations, ECSLKEY and EXEONLY locations are hardwired for 10 wait-

states. The RWAIT bits have no effect on these locations

CPU writes to the flash or OTP memory map areas are ignored. They complete in a single cycle.

If C28x security zone is in the locked state and the respective password lock bits are not all 1s, then,

– Data reads to C28X-Z1-CSMPSWD, C28x-Z1-ECSLPSWD will return 0.

– Program space reads to C28X-Z1-CSMPSWD, C28x-Z1-ECSLPSWD will return 0.

– Program fetches to C28X-Z1-CSMPSWD, C28x-Z1-ECSLPSWD will return 0.

When the code security module (CSM) is secured, reads to the flash/OTP memory map area from

outside the secure zone take the same number of cycles as a normal access. However, the read

operation returns a zero.

The arbitration scheme in C28x-FMC prioritizes C28x core accesses in the fixed priority order of data

read (highest priority), program space read and program fetches/program prefetches (lowest priority)

When FSM interface is active for erase/program operations, data in the prefetch buffers and data

cache in FMC will be flushed.

SPRUHE8E – October 2012 – Revised November 2019

Submit Documentation Feedback

Figure 5-83. Flash Prefetch Mode

Instruction buffer

Instruction fetch

Data read either from program or data memory

Flash or OTP Read (128-bit)

Flash Controller Memory Module

Flash and OTP

Internal Memory

Chapters

Table of Contents