Time-Base Control Register (Tbctl) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 7-32. Time-Base Control Register (TBCTL) Field Descriptions
Bit Field
15-14 FREE, SOFT
13 PHSDIR
12-10 CLKDIV
9-7 HSPCLKDIV
6 SWFSYNC
5-4 SYNCOSEL
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
emulation events:
00 Stop after the next time-base counter increment or decrement
01 Stop when counter completes a whole cycle:
• Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)
• Down-count mode: stop when the time-base counter = 0x00 (TBCTR = 0x00)
• Up-down-count mode: stop when the time-base counter = 0x00 (TBCTR = 0x00)
1X Free run
Phase Direction Bit.
This bit is only used when the time-base counter is configured in the up-down-count mode. The
PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization
event occurs and a new phase value is loaded from the phase (TBPHS) register. This is
irrespective of the direction of the counter before the synchronization event..
In the up-count and down-count modes this bit is ignored.
0 Count down after the synchronization event.
1 Count up after the synchronization event.
Time-base Clock Prescale Bits
These bits determine part of the time-base clock prescale value.
TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
000 /1 (default on reset)
001 /2
010 /4
011 /8
100 /16
101 /32
110 /64
111 /128
High Speed Time-base Clock Prescale Bits
These bits determine part of the time-base clock prescale value.
TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager
(EV) peripheral.
000 /1
001 /2 (default on reset)
010 /4
011 /6
100 /8
101 /10
110 /12
111 /14
Software Forced Synchronization Pulse
0 Writing a 0 has no effect and reads always return a 0.
1 Writing a 1 forces a one-time synchronization pulse to be generated.
This event is ORed with the EPWMxSYNCI input of the ePWM module.
SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00.
Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal.
00 EPWMxSYNC:
01 CTR = zero: Time-base counter equal to zero (TBCTR = 0x00)
10 CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB)
11 Disable EPWMxSYNCO signal
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C28 Enhanced Pulse Width Modulator (ePWM) Module
Registers
773