Adc Control Register 2 (Adcctl2) (Address Offset 01H); Adc Interrupt Flag Register (Adcintflg) (Address Offset 04H); Adc Control Register 2 (Adcctl2) Field Descriptions; Adc Interrupt Flag Register (Adcintflg) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Analog-to-Digital Converter (ADC)

Figure 10-18. ADC Control Register 2 (ADCCTL2) (Address Offset 01h)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10-7. ADC Control Register 2 (ADCCTL2) Field Descriptions

10.3.11.3 ADC Interrupt Registers

The registers and descriptions are shown below.

Figure 10-19. ADC Interrupt Flag Register (ADCINTFLG) (Address Offset 04h)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10-8. ADC Interrupt Flag Register (ADCINTFLG) Field Descriptions

(x = 8 to 1)

Analog Subsystem

ADCNONOVERLAP Control bit.

Overlap of sample and conversion is allowed.

Overlap of sample is not allowed.

When enabled, divides the ADC input clock by 2. When running /2 ADCCLK, scale the minimum

sample duration accordingly to meet 187ns for better throughput.

ADC clock = ACIB clock

ADC clock = ACIB clock/2

ADC Interrupt Flag Bits: Reading this bit indicates if an ADCINT pulse was generated

No ADC interrupt pulse generated

ADC Interrupt pulse generated

If the ADC interrupt is placed in continuous mode (INTSELxNy register) then further interrupt pulses

are generated whenever a selected EOC event occurs even if the flag bit is set.

If the continuous mode is not enabled, then no further interrupt pulses are generated until the user

clears this flag bit using the ADCINTFLGCLR register. The ADCINTOVF flag will be set if EOC

events are generated while the ADCINTFLG flag is set. Both ADCINTFLG and ADCINTOVF flags

must be cleared before normal interrupt operation can resume.

ADCNONOVERLAP

SPRUHE8E – October 2012 – Revised November 2019

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