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15.1.4 Data Transfer Process of McBSP
Figure 15-2
shows a diagram of the McBSP data transfer paths. The McBSP receive operation is triple-
buffered, and transmit operation is double-buffered. The use of registers varies, depending on whether the
defined length of each serial word is 16 bits.
RSR[1,2]
DR
XSR[1,2]
DX
15.1.4.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits
If the word length is 16 bits or smaller, only one 16-bit register is needed at each stage of the data transfer
paths. The registers DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted).
Receive data arrives on the DR pin and is shifted into receive shift register 1 (RSR1). Once a full word is
received, the content of RSR1 is copied to receive buffer register 1 (RBR1) if RBR1 is not full with
previous data. RBR1 is then copied to data receive register 1 (DRR1), unless the previous content of
DRR1 has not been read by the CPU or the DMA controller. If the companding feature of the McBSP is
implemented, the required word length is 8 bits and receive data is expanded into the appropriate format
before being passed from RBR1 to DRR1. For more details about reception, see
Transmit data is written by the CPU or the DMA controller to data transmit register 1 (DXR1). If there is no
previous data in transmit shift register (XSR1), the value in DXR1 is copied to XSR1; otherwise, DXR1 is
copied to XSR1 when the last bit of the previous data is shifted out on the DX pin. If selected, the
companding module compresses 16-bit data into the appropriate 8-bit format before passing it to XSR1.
After transmit frame synchronization, the transmitter begins shifting bits from XSR1 to the DX pin. For
more details about transmission, see
15.1.4.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits
If the word length is larger than 16 bits, two 16-bit registers are needed at each stage of the data transfer
paths. The registers DRR2, RBR2, RSR2, DXR2, and XSR2 are needed to hold the most significant bits.
Receive data arrives on the DR pin and is shifted first into RSR2 and then into RSR1. Once the full word
is received, the contents of RSR2 and RSR1 are copied to RBR2 and RBR1, respectively, if RBR1 is not
full. Then the contents of RBR2 and RBR1 are copied to DRR2 and DRR1, respectively, unless the
previous content of DRR1 has not been read by the CPU or the DMA controller. The CPU or the DMA
controller must read data from DRR2 first and then from DRR1. When DRR1 is read, the next RBR-to-
DRR copy occurs. For more details about reception, see
For transmission, the CPU or the DMA controller must write data to DXR2 first and then to DXR1. When
new data arrives in DXR1, if there is no previous data in XSR1, the contents of DXR2 and DXR1 are
copied to XSR2 and XSR1, respectively; otherwise, the contents of the DXRs are copied to the XSRs
when the last bit of the previous data is shifted out on the DX pin. After transmit frame synchronization,
the transmitter begins shifting bits from the XSRs to the DX pin. For more details about transmission, see
Section
15.3.6.
15.1.5 Companding (Compressing and Expanding) Data
Companding (COMpressing and exPANDing) hardware allows compression and expansion of data in
either μ-law or A-law format. The companding standard employed in the United States and Japan is μ-law.
The European companding standard is referred to as A-law. The specifications for μ-law and A-law log
PCM are part of the CCITT G.711 recommendation.
A-law and μ-law allow 13 bits and 14 bits of dynamic range, respectively. Any values outside this range
are set to the most positive or most negative value. Thus, for companding to work best, the data
transferred to and from the McBSP via the CPU or DMA controller must be at least 16 bits wide.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 15-2. McBSP Data Transfer Paths
Compand
RBR[1,2]
RBR[1,2]
Expand
Compress
Section
15.3.6.
Copyright © 2012–2019, Texas Instruments Incorporated
DRR[1,2]
DRR[1,2]
To CPU/DMA controller
DXR[1,2]
From CPU/DMA controller
Section
Section
15.3.5.
C28 Multichannel Buffered Serial Port (McBSP)
Overview
15.3.5.
1077
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