Uart Receive Status/Error Clear Register (Uartrsr/Uartecr); Uart Flag Register (Uartfr); Uart Error Clear (Uartecr) Register Field Descriptions; Uart Flag Register (Uartfr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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WRITE-ONLY Error Clear Register
Figure 21-9. UART Receive Status/Error Clear Register (UARTRSR/UARTECR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-4. UART Error Clear (UARTECR) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 DATA
21.7.3 UART Flag Register (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE
and RXFE bits are 1.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-8 Reserved
7 TXFE
6 RXFF
5 TXFF
4 RXFE
SPRUHE8E – October 2012 – Revised November 2019
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Reserved
W-0
Value Description
Reserved
Error Clear
A write to this register of any data clears the framing, parity, break, and overrun flags.
Figure 21-10. UART Flag Register (UARTFR)
R-0
Table 21-5. UART Flag Register (UARTFR) Field Descriptions
Value Description
Reserved
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.
0 The transmitter has data to transmit.
1 If the FIFO is disabled (FEN is 0), the transmit holding register is empty.
If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.
0 The receiver can receive data.
1 If the FIFO is disabled (FEN is 0), the receive holding register is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.
0 The transmitter is not full.
1 If the FIFO is disabled (FEN is 0), the transmit holding register is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.
0 The receiver is not empty.
1 If the FIFO is disabled (FEN is 0), the receive holding register is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
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Reserved
R-0
8 7 6 5
TXFE RXFF TXFF
R-1 R-0 R-0
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Register Descriptions
8 7
DATA
W-0
4 3 2
RXFE BUSY Reserved
R-1 R-0 R-0
0
16
0
1501