Oneshot Single Conversion - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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10.3.3.2 Trigger Operation
Each SOC can be configured to start on one of many input triggers. Multiple SOC's can be configured for
the same channel if desired. Following is a list of the available input triggers:
• Software
• CPU Timers 0/1/2 interrupts
• External GPIO through GPTRIP2SEL register
• ePWM1-9 SOCA and SOCB
See the ADCSOCxCTL Register Bit Definitions and the TRIGxSEL Register Bit Definitions for the
configuration details of these triggers.
Additionally ADCINT1 and ADCINT2 can be fed back to trigger another conversion. This configuration is
controlled in the ADCINTSOCSEL1/2 registers. This mode is useful if a continuous stream of conversions
is desired. See Section 10.3.7
10.3.3.3 Channel Selection
Each SOC can be configured to convert any of the available ADCIN input channels. When an SOC is
configured for sequential sampling mode, the four bit CHSEL field of the ADCSOCxCTL register defines
which channel to convert. When an SOC is configured for simultaneous sampling mode, the most
significant bit of the CHSEL field is dropped and the lower three bits determine which pair of channels are
converted.
10.3.4 ONESHOT Single Conversion Support
This mode will allow you to perform a single conversion on the next triggered SOC in the round robin
scheme. The ONESHOT mode is only valid for channels present in the round robin wheel. Channels
which are not configured for triggered SOC in the round robin scheme will get priority based on contents
of the SOCPRIORITY field in the ADCSOCPRIORITYCTL register.
The effect of ONESHOT mode on Sequential Mode and Simultaneous Mode is explained below.
Sequential mode: Only the next active SOC in RR mode (one up from current RR pointer) will be allowed
to generate SOC; all other triggers for other SOC slots will be ignored.
Simultaneous mode: If current RR pointer has SOC with simultaneous enabled; active SOC will be
incremented by 2 from the current RR pointer. This is because simultaneous mode will create result for
SOCx and SOCx+1, and SOCx+1 will never be triggered by the user.
SPRUHE8E – October 2012 – Revised November 2019
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for information on the ADC interrupt signals.
Figure 10-13. ONESHOT Single Conversion
Incoming ADC Trigger
No
ONESHOT ! = 0
Yes
Beginning with current Round Robin
Pointer, only set the SOCFLG
bit for next triggered sequence
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Analog-to-Digital Converter (ADC)
Process sampling
with current ADC
state machine
901
Analog Subsystem