Configurable Fault Status (Faultstat) Register; Configurable Fault Status (Faultstat) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Block (SCB) Register Descriptions
25.6.12 Configurable Fault Status (FAULTSTAT) Register, offset 0xD28
Note: This register can only be accessed from privileged mode.
The Configurable Fault Status (FAULTSTAT) register indicates the cause of a memory management fault,
bus fault, or usage fault. Each of these functions is assigned to a subregister as follows:
• Usage Fault Status (UFAULTSTAT), bits 31:16
• Bus Fault Status (BFAULTSTAT), bits 15:8
• Memory Management Fault Status (MFAULTSTAT), bits 7:0
FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows:
• The complete FAULTSTAT register, with a word access to offset 0xD28
• The MFAULTSTAT, with a byte access to offset 0xD28
• The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28
• The BFAULTSTAT, with a byte access to offset 0xD29
• The UFAULTSTAT, with a halfword access to offset 0xD2A
Bits are cleared by writing a 1 to them.
In a fault handler, the true faulting address can be determined by:
• Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address
(FAULTADDR) value.
• Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the
MMADDR or FAULTADDR contents are valid.
Software must follow this sequence because another higher priority exception might change the MMADDR
or FAULTADDR value. For example, if a higher priority handler preempts the current fault handler, the
other fault might change the MMADDR or FAULTADDR value.
31 30
23 22
Reserved
15 14
BFARV Reserved
R/W-1C-0
7 6
MMARV Reserved
R/W-1C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-50. Configurable Fault Status (FAULTSTAT) Register Field Descriptions
Bit Field
31-26 Reserved
25 DIV0
1680
Cortex-M3 Peripherals
Figure 25-43. Configurable Fault Status (FAULTSTAT) Register
29 28
Reserved
R-0
21 20
R-0
13 12
BSTKE
R-0 R/W-1C-0
5 4
MSTKE
R-0 R/W-1C-0
Value Description
Reserved
Divide-by-Zero Usage Fault
0 No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled.
1 The processor has executed an SDIV or UDIV instruction with a divisor of 0.
When this bit is set, the PC value stacked for the exception return points to the instruction that
performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the
Configuration and Control (CFGCTRL) register).
This bit is cleared by writing a 1 to it.
Copyright © 2012–2019, Texas Instruments Incorporated
27 26
19 18
NOCP INVPC
R/W-1C-0 R/W-1C-0
11 10
BUSTKE IMPRE
R/W-1C-0 R/W-1C-0
3 2
MUSTKE Reserved
R/W-1C-0 R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
25 24
DIV0 UNALIGN
R/W-1C-0 R/W-1C-0
17 16
INVSTAT UNDEF
R/W-1C-0 R/W-1C-0
9 8
PRECISE IBUS
R/W-1C-0 R/W-1C-0
1 0
DERR IERR
R/W-1C-0 R/W-1C-0
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