Peripheral Clock Control Register 2 (Pclkcr2); Peripheral Clock Control Register 2 (Pclkcr2) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 1-137. Peripheral Clock Control Register 1 (PCLKCR1) Register Field Descriptions (continued)
Bit Field
7-0 EPWMxENCLK
(n = 8-1)

1.13.7.32 Peripheral Clock Control Register 2 (PCLKCR2)

15
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-138. Peripheral Clock Control Register 2 (PCLKCR2) Register Field Descriptions
Bit Field
15-9 Reserved
8 EQEP3ENCLK
7-4 Reserved
3 EPWM12 Clock
Enable
2 EPWM11ENCLK
1 EPWM10ENCLK
0 EPWM9ENCLK
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
ePWM8-1 Clock Enables
When set, this enables the clock to the respective ePWM module.
0 Clock is disabled
1 Clock is enabled
Figure 1-127. Peripheral Clock Control Register 2 (PCLKCR2)
Reserved
R-0:0
4
R-0
Value Description
Reserved
eQEP3 Clock Enable
When set, this enables the clock to the eQEP3 module.
0 eQEP3 clock is disabled
1 eQEP3 clock is enabled
Reserved
EPWM12 Clock Enable: When set, this enables the clock to the EPWM12 module
0 EPWM12 clock is disabled
1 EPWM12 clock is enabled
EPWM11 Clock Enable: When set, this enables the clock to the EPWM11 module
0 EPWM11 clock is disabled
1 EPWM11 clock is enabled
EPWM10 Clock Enable: When set, this enables the clock to the EPWM10 module
0 EPWM10 clock is disabled
1 EPWM10 clock is enabled
ePWM9 Clock Enable
When set, this enables the clock to the ePWM9 module.
0 ePWM9 clock is disabled
1 ePWM9 clock is enabled
Copyright © 2012–2019, Texas Instruments Incorporated
3 2
EPWM12 Clock EPWM11ENCL
Enable K
R/W-0 R/W-0
System Control Registers
9 8
EQEP3ENCLK
R/W-0
1 0
EPWM10ENCL EPWM9ENCLK
K
R/W-0 R/W-0
System Control and Interrupts
251