C28X Sx Shram Configuration Register 1 (Csxsrcr1); C28X Sx Shram Configuration Register 1 (Csxsrcr1) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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RAM Control Module Registers

Table 5-55. C28x Sx SHRAM Master Select Register (CSxMSEL) Field Descriptions (continued)

C28x Sx SHRAM Configuration Register 1 (CSxSRCR1)

Figure 5-47. C28x Sx SHRAM Configuration Register 1 (CSxSRCR1)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-56. C28x Sx SHRAM Configuration Register 1 (CSxSRCR1) Field Descriptions

Internal Memory

Master Ownership for S0 RAM Block

M3 subsystem is master for S0 RAM block. M3 CPU/µDMA accesses are allowed based on the

setting of protection bits in the MSxSRCR register.

C28 subsystem is master for S0 RAM block. C28 CPU/DMA accesses are allowed based on the

setting of protection bits in the CSxSRCR register.

CPU Write Protection S3

C28x CPU write allowed to S3 RAM block.

C28x CPU write not allowed to S3 RAM block.

DMA Write Protection S3

C28x DMA write allowed to S3 RAM block.

C28x DMA write not allowed to S3 RAM block.

CPU Fetch Protection S3

C28x CPU Fetch allowed from S3 RAM block.

C28x CPU Fetch not allowed from S3 RAM block.

CPU Write Protection S2

C28x CPU write allowed to S2 RAM block.

C28x CPU write not allowed to S2 RAM block.

DMA Write Protection S2

C28x DMA write allowed to S2 RAM block.

C28x DMA write not allowed to S2 RAM block.

SPRUHE8E – October 2012 – Revised November 2019

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