Gpio Interrupt Mask (Gpioim) Register; Gpio Raw Interrupt Status (Gpioris) Register; Gpio Interrupt Mask (Gpioim) Register Field Descriptions; Gpio Raw Interrupt Status (Gpioris) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
4.1.6.6 GPIO Interrupt Mask (GPIOIM) Register, offset 0x410
The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts
that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt
signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt
controller. All bits are cleared by a reset.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-10. GPIO Interrupt Mask (GPIOIM) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 IME
4.1.6.7 GPIO Raw Interrupt Status (GPIORIS) Register, offset 0x414
The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt
condition occurs on the corresponding GPIO pin. If the corresponding bit in the GPIO Interrupt Mask
(GPIOIM) register is set, the interrupt is sent to the interrupt controller. Bits read as zero indicate that
corresponding input pins have not initiated an interrupt. A bit in this register can be cleared by writing a 1
to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-11. GPIO Raw Interrupt Status (GPIORIS) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 RIS
4.1.6.8 GPIO Masked Interrupt Status (GPIOMIS) Register, offset 0x418
The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the
corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no
interrupt has been generated, or the interrupt is masked.
360
General-Purpose Input/Output (GPIO)
Figure 4-9. GPIO Interrupt Mask (GPIOIM) Register
R-0
Value Description
Reserved
GPIO Interrupt Mask Enable
0 The interrupt from the corresponding pin is masked.
1 The interrupt from the corresponding pin is sent to the interrupt controller.
Figure 4-10. GPIO Raw Interrupt Status (GPIORIS) Register
R-0
Value Description
Reserved
GPIO Interrupt Raw Status
0 An interrupt condition has not occurred on the corresponding pin.
1 An interrupt condition has occurred on the corresponding pin.
A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7
Reserved
R-0
8 7
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
IME
R/W-0
RIS
R/W-0
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