Usb Control And Status Endpoint N Low Register (Usbcsrl[N]) In Otg B/Device Mode; Usb Control And Status Endpoint 0 Low Register(Usbcsrl[N]) In Otg B/Device Mode Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 18-49. USB Control and Status Endpoint n Low Register(USBCSRL[n])
Bit Field Value
0 RXRDY
0
1
USBCSRL0 in OTG B/Device mode is shown in
Figure 18-47. USB Control and Status Endpoint n Low Register (USBCSRL[n])
7 6
CLRDT STALLED
W1C-0 W1C-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-50. USB Control and Status Endpoint 0 Low Register(USBCSRL[n])
Bit Field Value
7 CLRDT
0
1
6 STALLED
0
1
5 STALL
0
1
4 FLUSH
0
1
3 DATAEND
0
1
2 OVER
0
1
SPRUHE8E – October 2012 – Revised November 2019
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in OTG A/Host Mode Field Descriptions (continued)
Description
Receive Packet Ready.
If the AUTOCLR bit in the USBRXCSRH[n] register is set, then the this bit is automatically cleared when
a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is
clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit
manually when the packet has been unloaded from the receive FIFO.
No data packet has been received.
Indicates that a data packet has been received. The EPn bit in the USBTXIS register is also set in this
situation.
in OTG B/Device Mode
5 4
STALL FLUSH
R/W-0 R-0
in OTG B/Device Mode Field Descriptions
Description
Clear Data Toggle
No effect
Writing a 1 to this bit clears the DT bit in the USBRXCSRH[n] register.
Endpoint Stalled. Software must clear this bit.
A STALL handshake has been transmitted.
A STALL handshake has been transmitted.
Send Stall. Software must clear this bit to terminate the STALL condition.
Note: This bit has no effect where the endpoint is being used for isochronous transfers.
No effect
Issues a STALL handshake.
Flush FIFO. The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint receive
FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. Note that if the FIFO is double-buffered,
FLUSH may have to be set twice to completely clear the FIFO.
No effect
Flushes the next packet from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit
is cleared.
Note: This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be
corrupted.
Data error. This bit is cleared when RXRDY is cleared.
Note: This bit is only valid when the endpoint is operating in Isochronous mode. In Bulk mode, it always
returns zero.
Normal operation
Indicates that RXRDY is set and the data packet has a CRC or bit-stuff error.
This bit is cleared automatically.
Overrun. Software must clear this bit.
Note: This bit is only valid when the endpoint is operating in Isochronous mode. In Bulk mode, it always
returns zero.
No overrun error
Indicates an OUT packet cannot be loaded into the receive FIFO.
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 18-47 and described in
3 2
DATAERR OVER
R/W-0 R/W-0
M3 Universal Serial Bus (USB) Controller
Register Descriptions
Table 18-50.
1 0
FULL RXRDY
R/W-0 R-0
1383