Master Subsystem Nmi Sources And Mnmiwd - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com
MNMIFLG[NMIINT]
NMI INT TO M3 CPU
Generate
Interrupt
Pulse
When
Input = 1
M3 SYSRESETREQ
M3 SSCLK
MMIWDPRD[15:0]
MNMI
Watchdog
MNMIWDCNT[15:0]
All the NMI sources except for the ACIBERR NMI shown in
There is no provision for the user to disable NMI sources that are enabled by default. The ACIBERR NMI
can be enabled by setting the ACIBERRE (bit 9) bit in the MNMICFG register. Once this bit is set in the
MNMICFG register, it cannot be cleared by the user, and only a master subsystem reset can clear it. See
the MNMICFG register for more details.
Whenever an NMI signal is generated, the respective bit in the MNMIFLG register is set. To aid in debug,
development, and testing, an MNMIFLGFRC register is provided. Setting these bits in this register will
force the NMI to the CPU core as shown in
details. When an NMI is triggered to the master CPU, an MNMIWD counter is triggered and begins
counting. It will reset the device when the MNMIWD counter reaches a programmed MNMIWD period
value. The MNMIWD counter will stop counting and reset back to zero once all the set MNMIFLG bits and
the NMIINT flag bit in the MNMIFLG register are cleared.
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Figure 1-3. Master Subsystem NMI Sources and MNMIWD
MNMIFLGCLR[ NMIINT ]
clear
Latch
set
OR
M3
NMIRS
Refer "Resets" Section
Figure
Copyright © 2012–2019, Texas Instruments Incorporated
MNMIFLG[EXTGPIO]
MNMIFLGCLR[EXTGPIO]
clear clear
Latch Latch
set set
MNMIFLG[CLOCKFAIL]
MNMIFLGCLR[
clear
Latch
set
MNMIFLG[C28PIENMIERR]
MNMIFLGCLR[
clear
Latch
set
MNMIFLG[C28NMIWDRST]
MNMIFLGCLR[
clear
Latch
set
MNMIFLG[ACIBERR]
MNMIFLGCLR[
clear
Latch
ACIBERRE
set
MNMIFLG[HWBISTERR]
MNMIFLGCLR[HWBISTERR]
clear
Latch
set
Figure 1-3 are enabled by default on reset.
1-3. Refer to the MNMIFLGFRC register for more
Exceptions and Interrupts Control
EXTGPIO EXTGPIO
MNMIFLGFRC[EXTGPIO]
CLOCKFAIL ]
CLOCKFAIL
MNIFLGFRC[ CLOCKFAIL
C28PIENMIERR ]
C28PIENMIERR
MNIFLGFRC[ C28PIENMIERR
C28NMIWDRESET ]
C28NMIWDRESET
MNIFLGFRC[ C28NMIWDRESET
ACIBERR ]
ACIBERR
MNIFLGFRC[ ACIBERR
HWBISTERR
MNIFLGFRC[HWBISTERR]
System Control and Interrupts
]
]
]
]
99