Source/Destination Wrap Step Size Registers (Src/Dst_Wrap_Step) - Eallow Protected; Source/Destination Wrap Count Register (Scr/Dst_Wrap_Count); Source/Destination Wrap Step Size Registers (Src/Dst_Wrap_Step); Source/Destination Wrap Count Register (Scr/Dst_Wrap_Count) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions

11.8.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)

The source/destination wrap count register (SCR/DST_WRAP_COUNT) is shown in
described in Table
Figure 11-24. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT)
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-19. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) Field
Bit Field
15-0 WRAPCOUNT
11.8.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) —
EALLOW Protected
The source/destination wrap step size register (SRC/DST_WRAP_STEP) are shown in
described in Table
Figure 11-25. Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP)
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-20. Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) Field
Bit Field
15-0 WRAPSTEP
978
C28 Direct Memory Access (DMA) Module
11-19.
WRAPCOUNT
Value Description
These bits indicate the current wrap counter value:
0x0000 Wrap complete
0x0001 1 burst left
0x0002 2 burst left
... ...
0xFFFF 65535 burst left
The above values represent the state of the counter at the HALT conditions.
11-20.
Value Description
These bits specify the source begin address pointer post-increment/decrement
step size after wrap counter expires:
0x0FFF Add 4095 to address
... ...
0x0002 Add 2 to address
0x0001 Add 1 to address
0x0000 No address change
0xFFFF Sub 1 from address
0xFFFE Sub 2 from address
... ...
0xF000 Sub 4096 from address
Only values from -4096 to 4095 are valid.
Copyright © 2012–2019, Texas Instruments Incorporated
R/W-0
Descriptions
WRAPSTEP
R/W-0
Descriptions
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Figure 11-24 and
0
Figure 11-25 and
0
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