Event-Trigger Submodule Showing Event Inputs And Prescaled Outputs; Event-Trigger Submodule Registers - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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ePWM Submodules

Figure 7-43. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs

CTR=Zero or PRD

From Digital Compare

(DC) Submodule

The key registers used to configure the event-trigger submodule are shown in

ETCNTINITCTL

ETSEL - This selects which of the possible events will trigger an interrupt or start an ADC conversion.

ETPS - This programs the event prescaling options mentioned above.

ETFLG - These are flag bits indicating status of the selected and prescaled events.

ETCLR - These bits allow you to clear the flag bits in the ETFLG register via software.

ETFRC - These bits allow software forcing of an event. Useful for debugging or software intervention.

ETINTPS - This programs the interrupt event prescaling options, supporting count and period up to 15

ETSOCPS - This programs the SOC event prescaling options, supporting count and period up to 15

ETCNTINITCTL - These bits enable ETCNTINIT initialization via SYNC event OR via software force.

ETCNTINIT - These bits allow you to initialize INT/SOCA/SOCB counters on SYNC events (or software

force) with user programmed value.

C28 Enhanced Pulse Width Modulator (ePWM) Module

Table 7-23. Event-Trigger Submodule Registers

Address Offset

Event Trigger

Module Logic

ETNTINITCTL reg

ETCNTINIT reg

Event-Trigger Selection Register

Event-Trigger Prescale Register

Event-Trigger Flag Register

Event-Trigger Clear Register

Event-Trigger Force Register

Event-Trigger Clear Register Mirror

Event-Trigger Interrupt Pre-Scale Register

Event-Trigger SOC Pre-Scale Register

Event-Trigger Counter Initialization Control Register

Event-Trigger Counter Initialization Register

SPRUHE8E – October 2012 – Revised November 2019

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