System Control Functional Description; Device Identification - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Functional Description

Pin Functional Pin Name(refer
Name to datasheet for
pin numbers)
Refer to the data
VREG12EN manual for pin
Refer to the data
Vssosc manual for pin
Refer to the data
EMU0 manual for pin
Refer to the data
EMU1 manual for pin
1.2 System Control Functional Description
The system control module provides the following capabilities:
• Device identification and configuration registers
• Reset control
• Device WIR mode control
• Exceptions and Interrupt control
• Safety and error handling features of the device
• Power control
• Clock control
• Low Power modes
• Security module
• Inter-Processor Communication (IPC)

1.2.1 Device Identification

Device identification registers provide information on device class, device family, revision, part number, pin
count, operating temperature range, package type, pin count and device qualification status.
All of the information is readable by master subsystem applications, and part number, part type and
revision information is readable by both the master subsystem and control subsystem. Please refer to the
System Control Registers section for more details on these registers.
1.2.1.1 Master Subsystem and Control Subsystem Device Identification
The master subsystem device identification registers are: DID0 and DID1. The control subsystem device
identification registers are: PARTID, REVID, and CDID.
82
System Control and Interrupts
Table 1-1. Signals for System Control and Clocks (continued)
Pin Mux/ Pin Assignment
Peripheral
Mode
Fixed
no.
Fixed
no.
Fixed
no.
Fixed
no.
Copyright © 2012–2019, Texas Instruments Incorporated
Alternate Mode Core Select
Select
Fixed Fixed
Fixed Fixed
Fixed Fixed
Fixed Fixed
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Description
Internal 1.2-V VREG Enable/Disable
for VDD12. Pull low to enable the
internal 1.2-V voltage regulator
(VREG12), pull high to disable
VREG12.
Clock Oscillator Ground Pin
Emulator pin 0. When TRST is
driven high, this pin is used as an
interrupt to or from the emulator
system and is defined as
input/output through the JTAG scan.
Emulator pin 1. When TRST is
driven high, this pin is used as an
interrupt to or from the emulator
system and is defined as
input/output through the JTAG scan.
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