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Clocking and Framing Data
Bits coming in on the DR pin are held in RSR until RSR holds a full serial word. Only then is the word
passed to RBR (and ultimately to the DRR).
During transmission, XSR does not accept new data from DXR until a full serial word has been passed
from XSR to the DX pin.
In the example in
Figure
transferred).
15.2.3 Frames and Frame Synchronization
One or more words are transferred in a group called a frame. You can define how many words are in a
frame.
All of the words in a frame are sent in a continuous stream. However, there can be pauses between frame
transfers. The McBSP uses frame-synchronization signals to determine when each frame is
received/transmitted. When a pulse occurs on a frame-synchronization signal, the McBSP begins
receiving/transmitting a frame of data. When the next pulse occurs, the McBSP receives/transmits the next
frame, and so on.
Pulses on the receive frame-synchronization (FSR) signal initiate frame transfers on DR. Pulses on the
transmit frame-sync (FSX) signal initiate frame transfers on DX. FSR or FSX can be derived from a pin at
the boundary of the McBSP or derived from inside the McBSP.
In the example in
Figure
occurs.
In McBSP operation, the inactive-to-active transition of the frame-synchronization signal indicates the start
of the next frame. For this reason, the frame-synchronization signal may be high for an arbitrary number of
clock cycles. Only after the signal is recognized to have gone inactive, and then active again, does the
next frame synchronization occur.
15.2.4 Generating Transmit and Receive Interrupts
The McBSP can send receive and transmit interrupts to the CPU to indicate specific events in the McBSP.
To facilitate detection of frame synchronization, these interrupts can be sent in response to frame-
synchronization pulses. Set the appropriate interrupt mode bits to 10b (for reception, RINTM = 10b; for
transmission, XINTM = 10b).
15.2.4.1 Detecting Frame-Synchronization Pulses, Even in Reset State
Unlike other serial port interrupt modes, this mode can operate while the associated portion of the serial
port is in reset (such as activating RINT when the receiver is in reset). In this case, FSRM/FSXM and
FSRP/FSXP still select the appropriate source and polarity of frame synchronization. Thus, even when the
serial port is in the reset state, these signals are synchronized to the CPU clock and then sent to the CPU
in the form of RINT and XINT at the point at which they feed the receiver and transmitter of the serial port.
Consequently, a new frame-synchronization pulse can be detected, and after this occurs the CPU can
take the serial port out of reset safely.
15.2.5 Ignoring Frame-Synchronization Pulses
The McBSP can be configured to ignore transmit and/or receive frame-synchronization pulses. To have
the receiver or transmitter recognize frame-synchronization pulses, clear the appropriate frame-
synchronization ignore bit (RFIG = 0 for the receiver, XFIG = 0 for the transmitter). To have the receiver or
transmitter ignore frame-synchronization pulses until the desired frame length or number of words is
reached, set the appropriate frame-synchronization ignore bit (RFIG = 1 for the receiver, XFIG = 1 for the
transmitter). For more details on unexpected frame-synchronization pulses, see one of the following
topics:
•
Unexpected Receive Frame-Synchronization Pulse (see
•
Unexpected Transmit Frame-Synchronization Pulse (see
You can also use the frame-synchronization ignore function for data packing (for more details, see
Section
15.11.2).
1080
C28 Multichannel Buffered Serial Port (McBSP)
15-7, an 8-bit word size was defined (see bits 7 through 0 of word B being
15-7, a one-word frame is transferred when a frame-synchronization pulse
Copyright © 2012–2019, Texas Instruments Incorporated
Section
15.5.3)
Section
15.5.5)
SPRUHE8E – October 2012 – Revised November 2019
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