M3 Sx Shram Configuration Register 1 (Msxsrcr1); M3 Sx Shram Configuration Register 1 (Msxsrcr1) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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RAM Control Module Registers

Table 5-18. Sx SHRAM Master Select Register (MSxMSEL) Field Descriptions (continued)

M3 Sx SHRAM Configuration Register 1 (MSxSRCR1)

Figure 5-10. M3 Sx SHRAM Configuration Register 1 (MSxSRCR1)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-19. M3 Sx SHRAM Configuration Register 1 (MSxSRCR1) Field Descriptions

Internal Memory

Master Ownership for S0 RAM Block

M3 subsystem is master for S0 RAM block. M3 CPU/µDMA accesses are allowed based on the

setting of protection bits in the MSxSRCR register.

C28 subsystem is master for S0 RAM block. C28 CPU/DMA accesses are allowed based on the

setting of protection bits in the CSxSRCR register.

CPU Write Protection S3

M3 CPU write allowed to S3 RAM block.

M3 CPU write not allowed to S3 RAM block.

µDMA Write Protection S3

M3 µDMA write allowed to S3 RAM block.

M3 µDMA write not allowed to S3 RAM block.

CPU Fetch Protection S3

M3 CPU Fetch allowed from S3 RAM block.

M3 CPU Fetch not allowed from S3 RAM block.

CPU Write Protection S2

M3 CPU write allowed to S2 RAM block.

M3 CPU write not allowed to S2 RAM block.

µDMA Write Protection S2

M3 µDMA write allowed to S2 RAM block.

M3 µDMA write not allowed to S2 RAM block.

SPRUHE8E – October 2012 – Revised November 2019

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