C28X Ram Configuration Registers Summary - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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MNMDMAWRAVADD

MMDMAWRAVADDR

C28RTESTINIT

CLxRTESTINIT1

CSxRTESTINIT1

C28RINITDONE

CLxRINITDONE1

CSxRINITDONE1

SPRUHE8E – October 2012 – Revised November 2019

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Table 5-10. M3 RAM Error Registers Summary (continued)

Table 5-11. C28x RAM Configuration Registers Summary

Offset (x16)

RAM Control Module Registers

Reset Source Register Description

M3 Uncorrectable Error Flag Clear Register

M3 Corrected Error Counter Register

M3 Corrected Error Threshold Register

M3 Corrected Error Threshold Exceeded Flag

M3 Corrected Error Threshold Exceeded Force

M3 Corrected Error Threshold Exceeded Flag

Clear Register

M3 Single Error Interrupt Enable Register

Non-Master Access Violation Flag Register

Non-Master Access Violation Flag Clear

Master Access Violation Flag Register

Master Access Violation Flag Clear Register

Non-Master CPU Write Access Violation

Address Register

Non-Master DMA Write Access Violation

Address Register

Non-Master CPU Fetch Access Violation

Address Register

Master CPU Write Access Violation Address

Master DMA Write Access Violation Address

Master CPU Fetch Access Violation Address

Reset Source Register Description

Lx DEDRAM Configuration Register 1

Lx SHRAM Configuration Register 1

C28x Sx SHRAM Master Select Register

C28x Sx SHRAM Configuration Register 1

C28x Sx SHRAM Configuration Register 2

C28TOC28_MSG_RAM Configuration Register

M0, M1 and C28T0C28_MSG_RAM Test and

Initialization Register

Lx RAM Test and Initialization Register 1

C28x Sx RAM Test and Initialization Register 1

M0, M1 and C28T0M3_MSG_RAM INIT Done

C28x Lx RAM_INIT_DONE Register 1

C28x Sx RAM_INIT_DONE Register 1

Internal Memory

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