Μdma Register Descriptions; Dma Status (Dmastat), Offset 0X000; Dma Status (Dmastat) Register; Dma Status (Dmastat) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

µDMA Register Descriptions
Alternate Memory Scatter-Gather
This value must be used in the alternate channel control data structure when the µDMA controller
operates in Memory Scatter-Gather mode.
Peripheral Scatter-Gather
This value must be used in the primary channel control data structure when the µDMA controller operates
in Peripheral Scatter-Gather mode. In this mode, the µDMA controller operates exactly the same as in
Memory Scatter-Gather mode, except that instead of performing the number of transfers specified by the
XFERSIZE field in the alternate control structure at one time, the µDMA controller only performs the
number of transfers specified by the ARBSIZE field per trigger; see Basic mode for details. See
Section 16.3.6.6.
Alternate Peripheral Scatter-Gather
This value must be used in the alternate channel control data structure when the µDMA controller
operates in Peripheral Scatter-Gather mode.
16.7 µDMA Register Descriptions
The register addresses given are relative to the µDMA base address of 0x400F.F000.

16.7.1 DMA Status (DMASTAT), offset 0x000

The DMA Status (DMASTAT) register returns the status of the µDMA controller. You cannot read this
register when the µDMA controller is in the reset state.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-21 Reserved
20-16 DMACHANS
15-8 Reserved
1212
M3 Micro Direct Memory Access ( µDMA)
Figure 16-10. DMA Status (DMASTAT) Register
Reserved
R-0
R-0
Table 16-17. DMA Status (DMASTAT) Register Field Descriptions
Value Description
Reserved
Available µDMA Channels Minus 1
This field contains a value equal to the number of µDMA channels the µDMA controller is
configured to use, minus one. The value of 0x1F corresponds to 32 µDMA channels.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
21
8 7
STATE
R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
20
DMACHANS
R-1F
4 3 1
Reserved
R-0
Submit Documentation Feedback
16
0
MAST
EN
R-0