Time-Base Submodule Signals And Registers; Key Time-Base Signals - Texas Instruments Concerto F28M36 Series Technical Reference Manual

ePWM Submodules
The block diagram in
Table 7-5 provides descriptions of the key signals associated with the time-base submodule.
TBCTR[15:0]
CTR = Zero
CTR_dir
CTR_max
TBCLK
SYSCLKOUT
Prescale
TBCTL[HSPCLKDIV]
TBCTL[CLKDIV]
A. These signals are generated by the digital compare (DC) submodule.
A These events are generated by the type 2 ePWM digital compare (DC) submodule based on the levels of the TRIPIN
inputs [For Example: COMPxOUT and TZ signals].
Signal Description
EPWMxSYNCI Time-base synchronization input.
Input pulse used to synchronize the time-base counter with the counter of ePWM module earlier in the
synchronization chain. An ePWM peripheral can be configured to use or ignore this signal. For the first ePWM
module (EPWM1) this signal comes from a device pin via GPTRIP6. For subsequent ePWM modules this
signal is passed from another ePWM peripheral. For example, EPWM2SYNCI is generated by the ePWM1
peripheral, EPWM3SYNCI is generated by ePWM2 and so forth. See
synchronization order of a particular device.
EPWMxSYNCO Time-base synchronization output.
This output pulse is used to synchronize the counter of an ePWM module later in the synchronization chain.
The ePWM module generates this signal from one of three event sources:
1. EPWMxSYNCI (Synchronization input pulse)
2. CTR = Zero: The time-base counter equal to zero (TBCTR = 0x00).
3. CTR = CMPB: The time-base counter equal to the counter-compare B (TBCTR = CMPB) register.
CTR = PRD Time-base counter equal to the specified period.
This signal is generated whenever the counter value is equal to the active period register value. That is when
TBCTR = TBPRD.
CTR = Zero Time-base counter equal to zero
This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x00.
682
C28 Enhanced Pulse Width Modulator (ePWM) Module
Figure 7-5 shows the critical signals and registers of the time-base submodule.
Figure 7-5. Time-Base Submodule Signals and Registers
TBPRD
Period Shadow
TBPRD
Period Active
16
16
Reset
Counter
Zero
TBCTL[CTRMODE]
UP/DOWN Mode
Dir
Load
Max
clk
TBCTR
Counter Active Reg
16
TBPHS
Phase Active Reg
Clock
TBCLK
Table 7-5. Key Time-Base Signals
Copyright © 2012–2019, Texas Instruments Incorporated
TBCTL[PRDLD]
TBCTL[SWFSYNC]
CTR = PRD
CTR = Zero
CTR = CMPB
TBCTL[PHSEN]
Disable
X
TBCTL[SYNCOSEL]
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
DCAEVT1.sync (A)
DCBEVT1.sync (A)
EPWMxSYNCI
Sync
EPWMxSYNCO
Out
Select
Section 7.2.2.3.3 for information on the
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