Epi Fifo Level Selects (Epififolvl) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 17-31. EPI FIFO Level Selects (EPIFIFOLVL) Register Field Descriptions
Bit Field
31-18 Reserved
17 WFERR
16 RSERR
15-7 Reserved
6-4 WRFIFO
0x5-0x7 Reserved
3 Reserved
2-0 RDFIFO
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Reserved
Write Full Error
0 The Write Full error interrupt is disabled. Writes are stalled when the WFIFO is full until a space
becomes available but an error is not generated. Note that the Cortex-M3 write buffer may hide that
stall if no other memory transactions are attempted during that time.
1 This bit enables the Write Full error interrupt (WTFULL in the EPIEISC register) to be generated
when a write is attempted and the WFIFO is full. The write stalls until a WFIFO entry becomes
available.
Read Stall Error
Note that the configuration of this bit has no effect on non-blocking reads.
0 The Read Stalled error interrupt is disabled. Reads behave as normal and are stalled until any
preceding writes have completed and the read has returned a result.
1 This bit enables the Read Stalled error interrupt (RSTALL in the EPIEISC register) to be generated
when a read is attempted and the WFIFO is not empty. The read is still stalled during the time the
WFIFO drains, but this error notifies the application that this excess delay has occurred.
Reserved
Write FIFO
This field configures the trigger point for the WFIFO.
0x0 Interrupt is triggered while WRFIFO is empty. It will be deasserted when not empty. This encoding
is optimized for burst of 4 writes
0x1 Reserved
0x2 Interrupt is triggered until there are only two slots available. Thus, trigger is deasserted when there
are two WRFIFO entries present. This configuration is optimized for bursts of 2 .
0x3 Interrupt is triggered until there is one WRFIFO entry available. This configuration expects only
single writes.
0x4 Trigger interrupt when WRFIFO is not full, meaning trigger will continue to assert until there are four
entries in the WRFIFO.
Reserved
Read FIFO
This field configures the trigger point for the NBRFIFO.
0x0 Reserved
0x1 Trigger when there are 1 or more entries in the NBRFIFO.
0x2 Trigger when there are 2 or more entries in the NBRFIFO.
0x3 Trigger when there are 4 or more entries in the NBRFIFO.
0x4 Trigger when there are 6 or more entries in the NBRFIFO.
0x5 Trigger when there are 7 or more entries in the NBRFIFO.
0x6 Trigger when there are 8 entries in the NBRFIFO.
0x7 Reserved
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Register Descriptions
External Peripheral Interface (EPI)
1293