Mpu Region Attribute And Size (Mpuattr) Register; Mpu Region Attribute And Size (Mpuattr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Memory Protection Unit (MPU) Register Descriptions
Figure 25-51. MPU Region Attribute and Size (MPUATTR) Register
31
Reserved
R-0
23 22
Reserved
R-0
15
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-59. MPU Region Attribute and Size (MPUATTR) Field Descriptions
Bit Field
31-29 Reserv ed
28 XN
27 Reserved
26-24 AP
23-22 Reserved
21-19 TEX
18 S
17 C
16 B
15-8 SRD
7-6 Reserved
5-1 SIZE
0 ENABLE
1690
Cortex-M3 Peripherals
29 28
XN
R/W-0
21
TEX
R/W-0
5
Value Description
Reserved
Instruction Access Disable
0 Instruction fetches are enabled.
1 Instruction fetches are disabled.
Reserved
Access Privilege
0 For information on using this bit field, see
Reserved
Type Extension Mask
0 For information on using this bit field, see
Shareable
0 For information on using this bit field, see
Cacheable
0 For information on using this bit field, see
Bufferable
0 For information on using this bit field, see
Subregion Disable Bits
0 The corresponding subregion is enabled.
1 The corresponding subregion is disabled.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such
a region, configure the SRD field as 0x00. See
Reserved
Region Size Mask
0 The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register.
Refer to Table 25-58 for more information
Region Enable
0 The region is disabled.
1 The region is enabled.
Copyright © 2012–2019, Texas Instruments Incorporated
27 26
Reserved
R-0
19 18
S
R/W-0
SRD
R/W-0
SIZE
R/W-0
Table 25-5.
Table 25-3.
Table 25-3.
Table 25-3.
Table 25-3.
Section 25.2.4.1.3
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
24
AP
R/W-0
17 16
C B
R/W-0 R/W-0
8
1 0
ENABLE
R/W-0
for more information.
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