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Memory Regions, Types and Attributes
24.6.6 Synchronization Primitives
The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a non-blocking
mechanism that a thread or process can use to obtain exclusive access to a memory location. Software
can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a
semaphore mechanism.
A pair of synchronization primitives consists of:
•
A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
•
A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained
exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the
thread or process did not gain exclusive access to the memory and no write is performed.
The pairs of load-exclusive and store-exclusive instructions are:
•
The word instructions LDREX and STREX
•
The halfword instructions LDREXH and STREXH
•
The byte instructions LDREXB and STREXB
Software must use a load-exclusive instruction with the corresponding store-exclusive instruction.
To perform a guaranteed read-modify-write of a memory location, software must:
•
Use a load-exclusive instruction to read the value of the location.
•
Update the value, as required.
•
Use a store-exclusive instruction to attempt to write the new value back to the memory location, and
test the returned status bit. If the status bit is clear, the read-modify-write completed successfully; if the
status bit is set, no write was performed, which indicates that the value returned at step 1 might be out
of date. The software must retry the read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
•
Use a load-exclusive instruction to read from the semaphore address to check whether the semaphore
is free.
•
If the semaphore is free, use a store-exclusive to write the claim value to the semaphore address.
•
If the returned status bit from step 2 indicates that the store-exclusive succeeded, then the software
has claimed the semaphore. However, if the store-exclusive failed, another process might have
claimed the semaphore after the software performed step 1.
The Cortex-M3 processor includes an exclusive access monitor that tags the fact that the processor has
executed a load-exclusive instruction. The processor removes its exclusive access tag if:
•
It executes a CLREX instruction.
•
It executes a store-exclusive instruction, regardless of whether the write succeeds.
•
An exception occurs, which means the processor can resolve semaphore conflicts between different
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Cortex-M3 Processor
Figure 24-13. Data Storage
Memory
7
0
Address A
B0
lsbyte
A+1
B1
A+2
B2
A+3
B3
msbyte
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