Gpio Masked Interrupt Status (Gpiomis) Register; Gpio Interrupt Clear (Gpioicr) Register; Gpio Masked Interrupt Status (Gpiomis) Register Field Descriptions; Gpio Interrupt Clear (Gpioicr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-12. GPIO Masked Interrupt Status (GPIOMIS) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 MIS
4.1.6.9 GPIO Interrupt Clear (GPIOICR) Register, offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt bit in the GPIORIS and GPIOMIS registers. Writing a 0 has no effect.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-13. GPIO Interrupt Clear (GPIOICR) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 IC
SPRUHE8E – October 2012 – Revised November 2019
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Figure 4-11. GPIO Masked Interrupt Status (GPIOMIS) Register
R-0
Value Description
Reserved
GPIO Masked Interrupt Status
0 An interrupt condition on the corresponding pin is masked or has not occurred.
1 An interrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller.
A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register.
Figure 4-12. GPIO Interrupt Clear (GPIOICR) Register
R-0
Value Description
Reserved
GPIO Interrupt Raw Status
0 The corresponding interrupt is unaffected.
1 The corresponding interrupt is cleared.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7
Reserved
R-0
8 7
General-Purpose Input/Output (GPIO)
General-Purpose Input/Output (GPIO)
MIS
R/W-0
IC
W/1C-0
16
0
16
0
361