Eqep Interrupt Clear (Qclr) Register; Eqep Interrupt Clear (Qclr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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eQEP Registers
Table 9-19. eQEP Interrupt Flag (QFLG) Register Field Descriptions (continued)
Bits Name
6
PCO
5
PCU
4
WTO
3
QDC
2
PHE
1
PCE
0
INT
15
Reserved
7
6
PCR
PCO
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-20. eQEP Interrupt Clear (QCLR) Register Field Descriptions
Bit
Field
15-12
Reserved
11
UTO
10
IEL
9
SEL
8
PCM
886
C28 Enhanced QEP (eQEP) Module
Value
Description
Position counter overflow interrupt flag
0
No interrupt generated
1
This bit is set on position counter overflow.
Position counter underflow interrupt flag
0
No interrupt generated
1
This bit is set on position counter underflow.
Watchdog timeout interrupt flag
0
No interrupt generated
1
Set by watch dog timeout
Quadrature direction change interrupt flag
0
No interrupt generated
1
This bit is set during change of direction
Quadrature phase error interrupt flag
0
No interrupt generated
1
Set on simultaneous transition of QEPA and QEPB
Position counter error interrupt flag
0
No interrupt generated
1
Position counter error
Global interrupt status flag
0
No interrupt generated
1
Interrupt was generated
Figure 9-38. eQEP Interrupt Clear (QCLR) Register
12
R-0
5
4
PCU
WTO
R/W-0
R/W-0
Value
Description
Always write as 0s
Clear unit time out interrupt flag
0
No effect
1
Clears the interrupt flag
Clear index event latch interrupt flag
0
No effect
1
Clears the interrupt flag
Clear strobe event latch interrupt flag
0
No effect
1
Clears the interrupt flag
Clear eQEP compare match event interrupt flag
0
No effect
1
Clears the interrupt flag
Copyright © 2012–2019, Texas Instruments Incorporated
11
10
UTO
IEL
R/W-0
R/W-0
3
2
QDC
PHE
R/W-0
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
9
8
SEL
PCM
R/W-0
R/W-0
1
0
PCE
INT
R/W-0
R/W-0
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