Ctomipc Communication - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Inter Processor Communications (IPC)
For every bit in the MTOCIPCSET register, there is a bit in the MTOCIPCCLR register. The M3 can set
bits in the MTOCIPCCLR register to clear corresponding flags (flag bit in MTOCIPCFLG and status bit in
MTOCIPCSTS) that the M3 has set previously using the MTOCIPCSET register. Generally, the C28x
should acknowledge the MTOCIPC request using the MTOCIPCACK register which will clear the
MTOCIPCFLG bits and MTOCIPCSTS bits. However, at times when the M3 did not receive any
acknowledgement from the C28x about the reception of a message in an expected duration, the M3
application software might want to clear the MTOCIPC flag request that it set earlier. In such a scenario,
the M3 can clear the flag requests that are raised previously by setting corresponding bits in the
MTOCIPCCLR register.
Out of the 32 MTOCIPC flags, the first four (bit 0 to bit 3) can generate corresponding MTOCIPC
interrupts (MTOCIPCINT1 to MTOCIPCINT4) to the C28x PIE if enabled. The remaining 28 bits (bit 4 to
bit 31) can be used as explained above in a software-based handshake (flag/ack) mechanism.
Note that the MTOCIPCSET registers are write-only by the M3 and will always read back as 0. The M3
should read the MTOCIPCFLG register to see pending requests. The MTOCIPCFLG and MTOCIPCSTS
registers are read-only and will always reflect the current status of the corresponding IPC flag whether it
has been requested or cleared. The MTOCIPCCLR and MTOCIPCACK bits are write-only and will always
read back as 0.

1.12.4 CTOMIPC Communication

When a message is ready for the C28x to send to the M3, the C28x can notify that to the M3 using
CTOMIPC flags or interrupts. The M3, upon polling for these CTOMIPC flags or upon getting a CTOMIPC
interrupt, can respond to the message sent by the C28x. There are three 32-bit registers: CTOMIPCSET,
CTOMIPCCLR and CTOMIPCFLG on the C28x memory map, and two 32-bit registers, CTOMIPCSTS
and CTOMIPCACK, to implement the flag-based message communication from the C28x to the M3. The
CTOMIPCSET register has 32 bits, each of which when set, is capable of enabling a corresponding flag
bit in the CTOMIPCFLG register on the C28x and a status bit in the CTOMIPCSTS register on the M3.
For example,
1. When the C28x wants to notify a message readiness to the M3, the C28x can set bit 9 (IPC flag 10) in
the CTOMIPCSET register.
2. This action of the C28x will result in setting bit 9 in the CTOMIPCSTS register on the M3 along with bit
9 in the CTOMIPCFLG register on the C28x. The CTOMIPCFLG register on the C28x and the
CTOMIPCSTS register on the M3 are physically the same but named differently as the FLG register on
the C28x and the STS register on the M3.
3. The M3 can poll for bit 9 (IPC flag 10) of the CTOMIPCSTS register while waiting for the message.
4. When bit 9 of the CTOMIPCSTS register gets set, the M3 can read the message if any or can take
necessary action depending on the design of the user application.
5. Then, the M3 should acknowledge the C28x that it received the CTOMIPC request by setting bit 9 of
the CTOMIPCACK register which will result in clearing bit 9 in the CTOMIPCFLG register and the
CTOMIPCSTS register.
Note that the CTOMIPCCLR register on the C28x and the CTOMIPCACK register on the M3 are
physically the same, but named differently as the CLR register on the C28x and the ACK register on
the M3.
For every bit in the CTOMIPCSET register, there is a bit in the CTOMIPCCLR register. The C28x can set
bits in the CTOMIPCCLR register to clear corresponding flags (flag bit in CTOMIPCFLG and status bit in
CTOMIPCSTS) that the C28x has set previously using the CTOMIPCSET register. Generally, the M3
should acknowledge a CTOMIPC request using the CTOMIPCACK register thus clearing the
CTOMIPCFLG and CTOMIPCSTS bits. However, at times when the C28x did not receive any
acknowledgement from the M3 about the reception of message in an expected duration, the C28x
application software might want to clear the CTOMIPC flag request that it set earlier. In such a scenario,
the C28x can clear the flag requests that it raised previously by setting the corresponding bits in the
CTOMIPCCLR register.
Out of the 32 CTOMIPC flags, the first four bits (bit 0 to bit 3) can generate corresponding CTOMIPC
interrupts (CTOMIPCINT1 to CTOMIPCINT4) to the M3 PIE if enabled. The remaining 28 bits (bit 4 to bit
31) can be used as explained above in a software-based handshake (flag/ack) mechanism.
160
System Control and Interrupts
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
www.ti.com