Mpu Region Base Address (Mpubase) Register Field Descriptions; Example Size Field Values - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 25-57. MPU Region Base Address (MPUBASE) Register Field Descriptions
Bit Field
31-5 ADDR
4 VALID
3 Reserved
2-0 REGION
25.7.5 MPU Region Attribute and Size (MPUATTR) Register, offset 0xDA0-DB8
The MPU Region Attribute and Size (MPUATTR) register defines the region size and memory attributes of
the MPU region specified by the MPU Region Number (MPUNUMBER) register and enables that region
and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant halfword
holding the region attributes and the least-significant halfword holds the region size and the region and
subregion enable bits.
The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the corresponding
memory region. If an access is made to an area of memory without the required permissions, then the
MPU generates a permission fault.
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register as
follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4.
example SIZE values with the corresponding region size and value of N in the MPU Region Base Address
(MPUBASE) register.
Note: This register can only be accessed from privileged mode.
SIZE Encoding
00100b (0x4)
01001b (0x9)
10011b (0x13)
11101b (0x1D)
11111b (0x1F)
(1)
Refers to the N parameter in the MPUBASE register
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Base Address Mask
Bits 31:N in this field contain the region base address. The value of N depends on the region size,
as shown above. The remaining bits (N-1):5 are reserved.
Software should not rely on the value of a reserved bit. To provide compatibility with future
products, the value of a reserved bit should be preserved across a read-modify-write operation.
Region Number Valid
0 The MPUNUMBER register is not changed and the processor updates the base address for the
region specified in the MPUNUMBER register and ignores the value of the REGION field.
1 The MPUNUMBER register is updated with the value of the REGION field and the base address is
updated for the region specified in the REGION field.
This bit is always read as 0.
Reserved
Region Number
On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the
current region number in the MPUNUMBER register
Table 25-58. Example SIZE Field Values
Region Size
32 B
1 KB
1 MB
1 GB
4 GB
Copyright © 2012–2019, Texas Instruments Incorporated
Memory Protection Unit (MPU) Register Descriptions
(1)
Value of N
5
10
20
30
No valid ADDR field in
MPUBASE; the region
occupies the complete memory
map.
Table 25-58 gives
Note
Minimum permitted size
-
-
-
Maximum possible size
1689
Cortex-M3 Peripherals