Gpio0 To Gpio31 Multiplexing Diagram - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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0 = PU disabled (reset value)
1 = PU enabled
PU
GPIOPUR
GPIOx
High
impedance
output
control
XRS
A GPxDAT latch/read are accessed at the same memory location.
B Pull-up selection is only controlled by the M3 GPIO registers exceptGPIO192-GPIO199, which is controlled by the
GPGPUD register.
Notes:
• Note the bit polarity difference between GPIOPUR and GPGPUD registers when enabling pullups.
• Open drain selection is only controlled by the M3 GPIO registers.
• The appropriate bits in the GPIOCSEL registers (M3 GPIO registers) must be set to use the C28
GPIOs. If the GPIO is set as an M3 GPIO, the C28 GPIO MUX inputs are still active and can be read.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 4-35. GPIO0 to GPIO31 Multiplexing Diagram
GPIOLPMSEL 1
LPMCR0
Low power
modes block
GPIOx.async
SYSCLKOUT
(B)
Sync
Qual
async
GPACTRL
GPAQSEL 1/2
GPAMUX 1/2
0 = input, 1 = output
Copyright © 2012–2019, Texas Instruments Incorporated
C28 General-Purpose Input/Output (GPIO)
GPTRIP4 (XINT1)
GPTRIP5 (XINT2)
GPTRIP6 (XINT3)
External
interrupt
MUX
(default
on reset)
00
00
3 samples
01 01
6 samples
10 10
11
11
2
(default on reset)
00
01
10
11
2
00
01
10
11
General-Purpose Input/Output (GPIO)
PIE
GPADAT (read)
(default on reset)
N/C
Peripheral 1 input
Peripheral 2 input
Peripheral 3 input
GPASET,
GPACLEAR,
GPATOGGLE
GPIOx_OUT
(A)
GPADAT
(latch)
Peripheral 1 output
Peripheral 2 output
Peripheral 3 output
(default on reset)
GPIOx_DIR
GPADIR
(latch)
Peripheral 1 output enable
Peripheral 2 output enable
Peripheral 3 output enable
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