Gptm Interrupt Mask (Gptmimr) Register, Offset 0X018; Gptm Interrupt Mask (Gptmimr) Register; Gptm Interrupt Mask (Gptmimr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
Table 2-8. GPTM Control (GPTMCTL) Register Field Descriptions (continued)
Bit Field
6 TAPWML
5 Reserved
4 RTCEN
3-2 TAEVENT
1 TASTALL
0 TAEN

2.6.5 GPTM Interrupt Mask (GPTMIMR) Register, offset 0x018

The GPTM Interrupt Mask (GPTMIMR) register allows software to enable/disable GPTM controller-level
interrupts. Setting a bit enables the corresponding interrupt, while clearing a bit disables it.
31
15
Reserved
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-9. GPTM Interrupt Mask (GPTMIMR) Register Field Descriptions
Bit Field
31-12
11 TBMIM
10 CBEIM
320
M3 General-Purpose Timers
Value Description
GPTM Timer A PWM Output Level
0 Output is unaffected.
1 Output is inverted.
Reserved
GPTM RTC Enable
0 RTC counting is disabled.
1 RTC counting is enabled.
GPTM Timer A Event Mode
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
GPTM Timer A Stall Enable
0 Timer A continues counting while the processor is halted by the debugger
1 Timer A freezes counting while the processor is halted by the debugger
GPTM Timer A Enable
0 Timer A is disabled
1 Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG
register.
Figure 2-10. GPTM Interrupt Mask (GPTMIMR) Register
12
R-0
5 4
TAMIM
R/W-0
Value Description
Reserved
GPTM Timer B Mode Match Interrupt Mask
0 Interrupt is disabled.
1 Interrupt is enabled.
GPTM Capture B Event Interrupt Mask
0 Interrupt is disabled.
1 Interrupt is enabled.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
11 10
TBMIM CBEIM
R/W-0 R/W-0
3 2
RTCIM CAEIM
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
9 8
CBMIM TBTOIM
R/W-0 R/W-0
1 0
CAMIM TATOIM
R/W-0 R/W-0
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