Set The Transmit Clock Mode; Set The Transmit Clock Polarity; Register Bit Used To Set The Transmit Clock Mode; How The Clkxm Bit Selects The Transmit Clock And The Corresponding Status Of The Mclkx Pin - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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When the sample rate generator comes out of reset, FSG is in its inactive state. Then, when GRST = 1
and FSGM = 1, a frame-synchronization pulse is generated. The frame width value (FWID + 1) is counted
down on every CLKG cycle until it reaches 0, at which time FSG goes low. At the same time, the frame
period value (FPER + 1) is also counting down. When this value reaches 0, FSG goes high, indicating a
new frame.

15.9.18 Set the Transmit Clock Mode

Register Bit
PCR 9
15.9.18.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
Table 15-67 shows how the CLKXM bit selects the transmit clock and the corresponding status of the
MCLKX pin. The polarity of the signal on the MCLKX pin is determined by the CLKXP bit.
Table 15-67. How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the
CLKXM in
PCR Source of Transmit Clock
0 Internal CLKX is driven by an external clock on the MCLKX pin.
CLKX is inverted as determined by CLKXP before being used.
1 Internal CLKX is driven by the sample rate generator clock,
CLKG.
15.9.18.2 Other Considerations
If the sample rate generator creates a clock signal (CLKG) that is derived from an external input clock, the
GSYNC bit determines whether CLKG is kept synchronized with pulses on the FSR pin. For more details,
see Section 15.4.3, Synchronizing Sample Rate Generator Outputs to an External Clock.
In the clock stop mode (CLKSTP = 10b or 11b), the McBSP can act as a master or as a slave in the SPI
protocol. If the McBSP is a master, make sure that CLKXM = 1 so that CLKX is an output to supply the
master clock to any slave devices. If the McBSP is a slave, make sure that CLKXM = 0 so that CLKX is an
input to accept the master clock signal.

15.9.19 Set the Transmit Clock Polarity

Register Bit
PCR 1
SPRUHE8E – October 2012 – Revised November 2019
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Table 15-66. Register Bit Used to Set the Transmit Clock Mode
Name Function
CLKXM Transmit clock mode
CLKXM = 0
CLKXM = 1
Table 15-68. Register Bit Used to Set Transmit Clock Polarity
Name Function
CLKXP Transmit clock polarity
CLKXP = 0 Transmit data sampled on rising edge of CLKX.
CLKXP = 1 Transmit data sampled on falling edge of CLKX.
Copyright © 2012–2019, Texas Instruments Incorporated
The transmitter gets its clock signal from an
external source via the MCLKX pin.
The MCLKX pin is an output pin driven by the
sample rate generator of the McBSP.
MCLKX pin
MCLKX pin Status
Input
Output. CLKG, inverted as determined by CLKXP,
is driven out on CLKX.
C28 Multichannel Buffered Serial Port (McBSP)
Transmitter Configuration
Reset
Type Value
R/W 0
Reset
Type Value
R/W 0
1149