Cepirtwcfg Register; Cepirtwcnt Register; Cepirtwcfg Register Field Descriptions; Cepirtwcnt Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 17-49. EPI Host-Bus 16 Timing Extension Register (EPIHB16TIME4) Field Descriptions (continued)
Bit Field
4 WRWSM
3-1 Reserved
0 RDWSM

17.11.37 CEPIRTWCFG Register

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit FiKEY
31-4 KEY
3-1 Reserved
0 GRAB

17.11.38 CEPIRTWCNT Register

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit FiKEY
31-0 EPIRTWCNT
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
CS3 Write Wait State Minus One
This bit is used with the WRWS field in EPIHB16CFG4. This field is not applicable in BURST mode.
0 No change in the number of wait state clock cycles programmed in the in WRWS field in
EPIHB16CFG4 register
1 Wait state value is now:
WRWS - 1
WRWS field is programmed in EPIHB16CFG4
Reserved
CS3 Read Wait State Minus One
Used with RDWS field in the EPIHB16CFG4 register. This field is not applicable in BURST mode.
0 No change in the number of wait state clock cycles programmed in the RDWS field of
EPIHB16CFG4
1 Wait state value is now:
RDWS - 1
RDWS field is programmed in EPIHB16CFG4
Figure 17-64. CEPIRTWCFG Register
KEY
R/W-0
Table 17-50. CEPIRTWCFG Register Field Descriptions
Value Description
This field should have value of "0x9EDCB4A" to enable write into the GRAB bit. During every write
to GRAB bit this field must have a valid value, hence the user always has to do a 32-bit write to
change the GRAB bit.
Reserved
Grabs the access for control subsystem (C28x-CPU/C28x-DMA). This bit gets reset to '0' when
TIMEOUT bit in CEPISTATUS register is set.
0 RTW feature is disabled. All the accesses to the external device via EPI are arbitrated based on
round robin scheme.
1 RTW feature is enabled. All the accesses from the Master subsystem (M3/uDMA) to the external
device via EPI are stalled until this bit is set to '1'.
Figure 17-65. CEPIRTWCNT Register
Table 17-51. CEPIRTWCNT Register Field Descriptions
Value Description
This is a free running counter which counts up for every cycle of C28x CPU CLK. This counter gets
enabled when the GRAB bit in the CEPIRTWCFG registers gets set to '1'. This counter gets reset
to 0x0 when GRAB bit in CEPIRTWCFG registers get reset to '0'.
Copyright © 2012–2019, Texas Instruments Incorporated
EPIRTWCNT
R-0
Register Descriptions
4 3 1
Reserved
R-0
External Peripheral Interface (EPI)
0
GRAB
R/W-0
0
1313