Control Subsystem Exceptions Handling; Control Subsystem Nmi (Cnmi) Module - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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1.5.5 Control Subsystem Exceptions Handling

The ITRAP (illegal exception trap condition) is the only type of exception (other than programmable

interrupts; TRAPs and NMI), which the control subsystem supports. An ITRAP exception occurs if an

illegal instruction is fetched and executed. On an ITRAP exception when the PIE is enabled, the program

counter is loaded with the vector address located at address location 0x00000D26. When the PIE is

disabled the vector address loaded in the program counter is fetched from the ROM Vector table location

NOTE: RAM Access Violation Interrupt (INT12.5):

PIE INT12.5 is defined for C28x RAM access violations, but for a fetch access violation,

the C28x will receive zero data and will ITRAP. The ITRAP occurs in the same cycle at

which the INT12.5 is fired to the C28x. Since the ITRAP has priority over normal interrupt,

the ITRAP ISR gets executed before the INT12.5 ISR. The user needs to take this into

account when servicing the ITRAP.

Please refer to the Boot ROM chapter for details on how the boot ROM handles this exception if it occurs

during its execution.

Similar to the MNMI module on the master subsystem, the control subsystem supports an NMI module

that enables it to detect serious errors that can occur during the operation of the device. Possible errors

that can trigger an NMI to the control subsystem are:

An NMI is generated to the control subsystem CPU if any of the above errors occur. If an NMI is triggered

to the control subsystem, the NMI WatchDog timer will start counting and will reset the control subsystem

if the counter value reaches a programmed period value. An NMI is generated to the Master CPU if the

control subsystem is reset by the control subsystem watchdog, CNsMIWD.

The C28x NMI block can be accessed via the C28x NMI configuration registers (including the CNMIFLG,

CNMIFLGCLR, and CNMIFLGFRC registers) to examine flag bits for the NMI sources, clear the flags, and

force the flags to active state, respectively.

explains how an NMI is generated to the control subsystem CPU.

SPRUHE8E – October 2012 – Revised November 2019

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Exceptions and Interrupts Control

System Control and Interrupts

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