Overview; Block Diagram - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Overview

16.1 Overview
The µDMA controller provides the following features:
• ARM PrimeCell® 32-channel configurable µDMA controller
• Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer
modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
• Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– Primary and secondary channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable bus arbitration scheme
– Optional software-initiated requests for any channel
• Two levels of priority
• Design optimizations for improved bus access performance between µDMA controller and the
processor core
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
• Data sizes of 8, 16, and 32 bits
• Transfer size is programmable in binary steps from 1 to 1024
• Source and destination address increment size of byte, half-word, word, or no increment
• Maskable peripheral requests

16.2 Block Diagram

Figure 16-1 illustrates the µDMA block diagram.
1186
M3 Micro Direct Memory Access ( µDMA)
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SPRUHE8E – October 2012 – Revised November 2019
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