Sleep Mode Clock Gating Control Register 0 (Scgc0); Deep Sleep Mode Clock Gating Control Register 0 (Dcgc0); Sleep Mode Clock Gating Control Register 0 (Scgc0) Field Descriptions; Deep Sleep Mode Clock Gating Control Register 0 (Dcgc0) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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1.13.7.14 Sleep Mode Clock Gating Control Register 0 (SCGC0)

Figure 1-109. Sleep Mode Clock Gating Control Register 0 (SCGC0)
31 29 28 27
Reserved WDT1
R-0:0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-120. Sleep Mode Clock Gating Control Register 0 (SCGC0) Field Descriptions
Bit Field
31-29 Reserved
28 WDT1
27-4 Reserved
3 WDT0
2-0 Reserved

1.13.7.15 Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)

Figure 1-110. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
31 29 28 27
Reserved WDT1
R-0:0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-121. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Field Descriptions
Bit Field
31-29 Reserved
28 WDT1
27-4 Reserved
3 WDT0
2-0 Reserved
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Reserved
WDT1 Clock Gating Control in Sleep Mode
This bit controls the clock gating for the WDT1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
WDT0 Clock Gating Control in Sleep Mode
This bit controls the clock gating for the WDT0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
Value Description
Reserved
WDT1 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the WDT1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
WDT0 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the WDT0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
Reserved
R-0:0
System Control Registers
4 3 2
WDT0 Reserved
R/W-0 R-0:0
4 3 2
WDT0 Reserved
R/W-0 R-0:0
System Control and Interrupts
0
0
233