An Unexpected Frame-Synchronization Pulse During A Mcbsp Reception - Texas Instruments Concerto F28M36 Series Technical Reference Manual

McBSP Exception/Error Conditions
pulse is not unexpected. There are three possible reasons why a receive operation might not be in
progress when the pulse occurs:
– The FSR pulse is the first after the receiver is enabled (RRST = 1 in SPCR1).
– The FSR pulse is the first after DRR[1,2] is read, clearing a receiver full (RFULL = 1 in SPCR1)
condition.
– The serial port is in the interpacket intervals. The programmed data delay for reception
(programmed with the RDATDLY bits in RCR2) may start during these interpacket intervals for the
first bit of the next word to be received. Thus, at maximum frame frequency, frame synchronization
can still be received 0 to 2 clock cycles before the first bit of the synchronized frame.
• Case 3: Unexpected receive frame synchronization with RFIG = 0 (frame-synchronization pulses not
ignored). Unexpected frame-synchronization pulses can originate from an external source or from the
internal sample rate generator.
If a frame-synchronization pulse starts the transfer of a new frame before the current frame is fully
received, this pulse is treated as an unexpected frame-synchronization pulse, and the receiver sets the
receive frame-synchronization error bit (RSYNCERR) in SPCR1. RSYNCERR can be cleared only by a
receiver reset or by a write of 0 to this bit.
If you want the McBSP to notify the CPU of receive frame-synchronization errors, you can set a special
receive interrupt mode with the RINTM bits of SPCR1. When RINTM = 11b, the McBSP sends a
receive interrupt (RINT) request to the CPU each time that RSYNCERR is set.
15.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
Figure 15-24 shows an unexpected receive frame-synchronization pulse during normal operation of the
serial port, with time intervals between data packets. When the unexpected frame-synchronization pulse
occurs, the RSYNCERR bit is set, the reception of data B is aborted, and the reception of data C begins.
In addition, if RINTM = 11b, the McBSP sends a receive interrupt (RINT) request to the CPU.
Figure 15-24. An Unexpected Frame-Synchronization Pulse During a McBSP Reception
CLKR
FSR
A1
DR
RRDY
RBR1 to DRR1 copy(A)
RSYNCERR
15.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
Each frame transfer can be delayed by 0, 1, or 2 MCLKR cycles, depending on the value in the RDATDLY
bits of RCR2. For each possible data delay,
on FSR can safely occur relative to the last bit of the current frame.
1096
C28 Multichannel Buffered Serial Port (McBSP)
A0 B7 B6 B5
Read from DRR1(A)
Figure 15-25
Copyright © 2012–2019, Texas Instruments Incorporated
Unexpected frame synchronization
B4 C7 C6 C5 C4 C3 C2
RBR1 to DRR1 copy(C)
shows when a new frame-synchronization pulse
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
C1 C0
RBR1 to DRR1(B)
Read from DRR1(C)
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